mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2024-12-28 23:29:58 +00:00
Initial checking of Z80 work; slight refactor of BusMonCore; version updated to 0.41
Change-Id: I95f574abb93e84ffb5ca44c45b4c9aa8304e2e58
This commit is contained in:
parent
eec6e10440
commit
9a68d96233
21
.gitignore
vendored
21
.gitignore
vendored
@ -5,5 +5,26 @@ AtomBusMon_guide.ncd
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AtomBusMon_summary.html
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src/AtomBusMon_bd.bmm
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src/AtomCpuMon_bd.bmm
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src/AtomCpuMon_bd.bmm
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src/Z80CpuMon_bd.bmm
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*~
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#*
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firmware/*.o
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firmware/*.bit
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firmware/avr_progmem.*
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ipcore_dir/WatchEvents.asy
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ipcore_dir/WatchEvents.gise
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ipcore_dir/WatchEvents.ncf
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ipcore_dir/WatchEvents.ngc
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ipcore_dir/WatchEvents.sym
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ipcore_dir/WatchEvents.vho
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ipcore_dir/WatchEvents.xco
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ipcore_dir/WatchEvents/
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ipcore_dir/WatchEvents_flist.txt
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ipcore_dir/WatchEvents_xmdf.tcl
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ipcore_dir/_xmsgs/
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ipcore_dir/coregen.cgp
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ipcore_dir/coregen.log
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ipcore_dir/create_WatchEvents.tcl
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ipcore_dir/edit_WatchEvents.tcl
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ipcore_dir/tmp/
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588
Z80CpuMon.xise
Normal file
588
Z80CpuMon.xise
Normal file
@ -0,0 +1,588 @@
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- -->
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||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
|
||||
</file>
|
||||
<file xil_pn:name="src/Z80CpuMon.bmm" xil_pn:type="FILE_BMM">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s250e" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
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|
||||
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|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
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|
||||
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|
||||
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|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
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|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
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|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
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|
||||
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|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Z80CpuMon" xil_pn:valueState="non-default"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
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|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
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|
||||
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|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="Z80CpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Z80CpuMon_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="Z80CpuMon_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Z80CpuMon_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Z80CpuMon_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Z80CpuMon" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="Z80CpuMon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-23T12:17:55" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="614C752717807585A7E3847C608873AC" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
@ -7,7 +7,14 @@
|
||||
#include "hd44780.h"
|
||||
#include "status.h"
|
||||
|
||||
#ifdef EMBEDDED_6502
|
||||
|
||||
#if (CPU == Z80)
|
||||
#define NAME "ICE-T80"
|
||||
#else
|
||||
#define NAME "ICE-T65"
|
||||
#endif
|
||||
|
||||
#ifdef CPUEMBEDDED
|
||||
|
||||
unsigned int disMem(unsigned int addr);
|
||||
|
||||
@ -330,15 +337,19 @@ char *triggerStrings[NUM_TRIGGERS] = {
|
||||
};
|
||||
|
||||
|
||||
#define VERSION "0.37"
|
||||
#define VERSION "0.41"
|
||||
|
||||
#ifdef EMBEDDED_6502
|
||||
#ifdef CPUEMBEDDED
|
||||
#define NUM_CMDS 27
|
||||
#else
|
||||
#define NUM_CMDS 19
|
||||
#endif
|
||||
|
||||
#if (CPU == Z80)
|
||||
#define MAXBKPTS 1
|
||||
#else
|
||||
#define MAXBKPTS 8
|
||||
#endif
|
||||
|
||||
int numbkpts = 0;
|
||||
|
||||
@ -350,6 +361,7 @@ unsigned int memAddr = 0;
|
||||
char statusString[8] = "NV-BDIZC";
|
||||
|
||||
unsigned int breakpoints[MAXBKPTS] = {
|
||||
#if (CPU != Z80)
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -357,10 +369,12 @@ unsigned int breakpoints[MAXBKPTS] = {
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
#endif
|
||||
0
|
||||
};
|
||||
|
||||
unsigned int masks[MAXBKPTS] = {
|
||||
#if (CPU != Z80)
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -368,10 +382,12 @@ unsigned int masks[MAXBKPTS] = {
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
#endif
|
||||
0
|
||||
};
|
||||
|
||||
unsigned int modes[MAXBKPTS] = {
|
||||
#if (CPU != Z80)
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -379,10 +395,12 @@ unsigned int modes[MAXBKPTS] = {
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
#endif
|
||||
0
|
||||
};
|
||||
|
||||
int triggers[MAXBKPTS] = {
|
||||
#if (CPU != Z80)
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -390,6 +408,7 @@ int triggers[MAXBKPTS] = {
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
#endif
|
||||
0
|
||||
};
|
||||
|
||||
@ -397,7 +416,7 @@ int triggers[MAXBKPTS] = {
|
||||
char *cmdStrings[NUM_CMDS] = {
|
||||
"help",
|
||||
"continue",
|
||||
#ifdef EMBEDDED_6502
|
||||
#ifdef CPUEMBEDDED
|
||||
"regs",
|
||||
"mem",
|
||||
"dis",
|
||||
@ -515,8 +534,13 @@ void setTrace(long i) {
|
||||
}
|
||||
|
||||
void version() {
|
||||
log0("Atom Bus Monitor version %s\n", VERSION);
|
||||
#ifdef CPUEMBEDDED
|
||||
log0("%s In-Circuit Emulator version %s\n", NAME, VERSION);
|
||||
#else
|
||||
log0("%s Bus Monitor version %s\n", NAME, VERSION);
|
||||
#endif
|
||||
log0("Compiled at %s on %s\n",__TIME__,__DATE__);
|
||||
log0("%d watches/breakpoints implemented\n",MAXBKPTS);
|
||||
}
|
||||
|
||||
|
||||
@ -606,7 +630,6 @@ int logDetails() {
|
||||
}
|
||||
logMode(mode);
|
||||
log0(" hit at %04X", i_addr);
|
||||
if (mode & BW_MEM_MASK) {
|
||||
if (mode & W_MEM_MASK) {
|
||||
log0(" writing");
|
||||
} else {
|
||||
@ -616,19 +639,16 @@ int logDetails() {
|
||||
if (mode & B_MASK) {
|
||||
logCycleCount(OFFSET_BW_CNTL, OFFSET_BW_CNTH);
|
||||
}
|
||||
#ifdef EMBEDDED_6502
|
||||
#ifdef CPUEMBEDDED
|
||||
if (mode & B_MEM_MASK) {
|
||||
// It's only safe to do this for brkpts, as it makes memory accesses
|
||||
disMem(i_addr);
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
log0("\n");
|
||||
}
|
||||
return watch;
|
||||
}
|
||||
|
||||
#ifdef EMBEDDED_6502
|
||||
#ifdef CPUEMBEDDED
|
||||
void loadData(unsigned int data) {
|
||||
int i;
|
||||
for (i = 0; i <= 7; i++) {
|
||||
@ -756,7 +776,7 @@ void logAddr() {
|
||||
#endif
|
||||
// Update the serial console
|
||||
logCycleCount(OFFSET_CNTL, OFFSET_CNTH);
|
||||
#ifdef EMBEDDED_6502
|
||||
#ifdef CPUEMBEDDED
|
||||
//log0("%04X\n", i_addr);
|
||||
disMem(memAddr);
|
||||
#else
|
||||
@ -793,7 +813,7 @@ void doCmdStep(char *params) {
|
||||
|
||||
j = trace;
|
||||
for (i = 1; i <= instructions; i++) {
|
||||
// Step the 6502
|
||||
// Step the CPU
|
||||
hwCmd(CMD_STEP, 0);
|
||||
if (i == instructions || (trace && (--j == 0))) {
|
||||
Delay_us(10);
|
||||
@ -804,7 +824,7 @@ void doCmdStep(char *params) {
|
||||
}
|
||||
|
||||
void doCmdReset(char *params) {
|
||||
log0("Resetting 6502\n");
|
||||
log0("Resetting CPU\n");
|
||||
hwCmd(CMD_RESET, 1);
|
||||
Delay_us(50);
|
||||
hwCmd(CMD_STEP, 0);
|
||||
@ -812,15 +832,15 @@ void doCmdReset(char *params) {
|
||||
hwCmd(CMD_RESET, 0);
|
||||
}
|
||||
|
||||
#ifdef EMBEDDED_6502
|
||||
#ifdef CPUEMBEDDED
|
||||
void doCmdRegs(char *params) {
|
||||
int i;
|
||||
log0("6502 Registers:\n");
|
||||
log0(" A=%02X X=%02X Y=%02X SP=01%02X PC=%04X\n",
|
||||
log0("CPU Registers:\n");
|
||||
log0(" A=%02X X=%02X Y=%02X SP=%04X PC=%04X\n",
|
||||
hwRead8(OFFSET_REG_A),
|
||||
hwRead8(OFFSET_REG_X),
|
||||
hwRead8(OFFSET_REG_Y),
|
||||
hwRead8(OFFSET_REG_SPL),
|
||||
hwRead16(OFFSET_REG_SPL),
|
||||
hwRead16(OFFSET_REG_PCL));
|
||||
unsigned int p = hwRead8(OFFSET_REG_P);
|
||||
char *sp = statusString;
|
||||
@ -1210,9 +1230,8 @@ void doCmdContinue(char *params) {
|
||||
#ifdef LCD
|
||||
unsigned int i_addr;
|
||||
#endif
|
||||
|
||||
// Step the 6502, otherwise the breakpoint happends again immediately
|
||||
hwCmd(CMD_STEP, 0);
|
||||
int reset = 0;
|
||||
sscanf(params, "%d", &reset);
|
||||
|
||||
// Disable breakpoints to allow loading
|
||||
hwCmd(CMD_BRKPT_ENABLE, 0);
|
||||
@ -1225,14 +1244,25 @@ void doCmdContinue(char *params) {
|
||||
shiftBreakpointRegister(0, 0, 0, 0);
|
||||
}
|
||||
|
||||
// Step the 6502, otherwise the breakpoint happends again immediately
|
||||
hwCmd(CMD_STEP, 0);
|
||||
|
||||
// Enable breakpoints
|
||||
hwCmd(CMD_BRKPT_ENABLE, 1);
|
||||
|
||||
// Disable single stepping
|
||||
setSingle(0);
|
||||
|
||||
// Reset if required
|
||||
if (reset) {
|
||||
log0("Resetting CPU\n");
|
||||
hwCmd(CMD_RESET, 1);
|
||||
Delay_us(100);
|
||||
hwCmd(CMD_RESET, 0);
|
||||
}
|
||||
|
||||
// Wait for breakpoint to become active
|
||||
log0("6502 free running...\n");
|
||||
log0("CPU free running...\n");
|
||||
int cont = 1;
|
||||
do {
|
||||
// Update the LCD display
|
||||
@ -1268,7 +1298,6 @@ void doCmdContinue(char *params) {
|
||||
logAddr();
|
||||
}
|
||||
|
||||
|
||||
void initialize() {
|
||||
CTRL_DDR = 255;
|
||||
STATUS_DDR = MUXSEL_MASK;
|
||||
@ -1289,7 +1318,7 @@ void initialize() {
|
||||
void (*cmdFuncs[NUM_CMDS])(char *params) = {
|
||||
doCmdHelp,
|
||||
doCmdContinue,
|
||||
#ifdef EMBEDDED_6502
|
||||
#ifdef CPUEMBEDDED
|
||||
doCmdRegs,
|
||||
doCmdMem,
|
||||
doCmdDis,
|
||||
|
@ -23,16 +23,14 @@ F_CPU=15855484
|
||||
CC=avr-gcc
|
||||
OBJCOPY=avr-objcopy
|
||||
|
||||
CFLAGS=-DEMBEDDED_6502=1 -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
|
||||
CFLAGS=-DCPU=6502 -DCPUEMBEDDED -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
|
||||
|
||||
OBJECTS=AtomBusMon.o hd44780.o status.o
|
||||
|
||||
load: avr.bit
|
||||
# sudo $(PROG) -v -f avr.bit
|
||||
# sudo $(PROG) -v -b $(BSCAN) -f avr.bit -sa -r
|
||||
build: avr6502cpu.bit
|
||||
|
||||
avr.bit: avr_progmem.mem
|
||||
$(DATA2MEM) -bm $(BMM_FILE) -bd avr_progmem.mem -bt $(BIT_FILE) -o b avr.bit
|
||||
avr6502cpu.bit: avr_progmem.mem
|
||||
$(DATA2MEM) -bm $(BMM_FILE) -bd avr_progmem.mem -bt $(BIT_FILE) -o b avr6502cpu.bit
|
||||
|
||||
avr_progmem.mem: avr_progmem.hex
|
||||
$(SREC_CAT) $< -Intel -Byte_Swap 2 -Data_Only -o tmp.mem -vmem 8
|
||||
@ -52,4 +50,4 @@ avr_progmem.out : $(OBJECTS)
|
||||
.phony: clean
|
||||
|
||||
clean:
|
||||
rm -f avr.bit avr_progmem.mem avr_progmem.hex avr_progmem.out avr_progmem.map *.o
|
||||
rm -f avr6502cpu.bit avr_progmem.mem avr_progmem.hex avr_progmem.out avr_progmem.map *.o
|
@ -23,23 +23,20 @@ F_CPU=15855484
|
||||
CC=avr-gcc
|
||||
OBJCOPY=avr-objcopy
|
||||
|
||||
CFLAGS=-DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
|
||||
CFLAGS=-DCPU=6502 -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
|
||||
|
||||
OBJECTS=AtomBusMon.o hd44780.o status.o
|
||||
|
||||
load: avr.bit
|
||||
# sudo $(PROG) -v -f avr.bit
|
||||
# sudo $(PROG) -v -b $(BSCAN) -f avr.bit -sa -r
|
||||
build: avr6502mon.bit
|
||||
|
||||
avr.bit: avr_progmem.mem
|
||||
$(DATA2MEM) -bm $(BMM_FILE) -bd avr_progmem.mem -bt $(BIT_FILE) -o b avr.bit
|
||||
avr6502mon.bit: avr_progmem.mem
|
||||
$(DATA2MEM) -bm $(BMM_FILE) -bd avr_progmem.mem -bt $(BIT_FILE) -o b avr6502mon.bit
|
||||
|
||||
avr_progmem.mem: avr_progmem.hex
|
||||
$(SREC_CAT) $< -Intel -Byte_Swap 2 -Data_Only -o tmp.mem -vmem 8
|
||||
$(GAWK) ' BEGIN{FS=" ";} { $$1= ""; print}' tmp.mem > $@
|
||||
rm tmp.mem
|
||||
|
||||
|
||||
avr_progmem.hex : avr_progmem.out
|
||||
$(OBJCOPY) -R .eeprom -O ihex avr_progmem.out avr_progmem.hex
|
||||
avr_progmem.out : $(OBJECTS)
|
||||
@ -52,4 +49,4 @@ avr_progmem.out : $(OBJECTS)
|
||||
.phony: clean
|
||||
|
||||
clean:
|
||||
rm -f avr.bit avr_progmem.mem avr_progmem.hex avr_progmem.out avr_progmem.map *.o
|
||||
rm -f avr6502mon.bit avr_progmem.mem avr_progmem.hex avr_progmem.out avr_progmem.map *.o
|
52
firmware/Makefile.z80cpu
Normal file
52
firmware/Makefile.z80cpu
Normal file
@ -0,0 +1,52 @@
|
||||
# Paths that will need changing
|
||||
|
||||
ATOMFPGA=$(HOME)/atom/AtomBusMon
|
||||
PAPILIO_LOADER=/opt/GadgetFactory/papilio-loader/programmer
|
||||
XILINX=/opt/Xilinx/14.7
|
||||
|
||||
# Shouldn't need to make changes below this point
|
||||
|
||||
BIT_FILE=$(ATOMFPGA)/working/Z80CpuMon.bit
|
||||
BMM_FILE=$(ATOMFPGA)/src/Z80CpuMon_bd.bmm
|
||||
|
||||
|
||||
# Papilio dev environment
|
||||
PROG=${PAPILIO_LOADER}/linux32/papilio-prog
|
||||
BSCAN=${PAPILIO_LOADER}/bscan_spi_xc3s500e.bit
|
||||
SREC_CAT=srec_cat
|
||||
GAWK=gawk
|
||||
DATA2MEM=${XILINX}/ISE_DS/ISE/bin/lin/data2mem
|
||||
|
||||
# AVR dev environment
|
||||
MCU=atmega103
|
||||
F_CPU=15855484
|
||||
CC=avr-gcc
|
||||
OBJCOPY=avr-objcopy
|
||||
|
||||
CFLAGS=-DCPU=Z80 -DCPUEMBEDDED -DF_CPU=${F_CPU}UL -DSERIAL_STATUS -DCOOKED_SERIAL -DNOUSART1 -mmcu=$(MCU) -Wall -Os -mcall-prologues
|
||||
|
||||
OBJECTS=AtomBusMon.o hd44780.o status.o
|
||||
|
||||
build: avrz80cpu.bit
|
||||
|
||||
avrz80cpu.bit: avr_progmem.mem
|
||||
$(DATA2MEM) -bm $(BMM_FILE) -bd avr_progmem.mem -bt $(BIT_FILE) -o b avrz80cpu.bit
|
||||
|
||||
avr_progmem.mem: avr_progmem.hex
|
||||
$(SREC_CAT) $< -Intel -Byte_Swap 2 -Data_Only -o tmp.mem -vmem 8
|
||||
$(GAWK) ' BEGIN{FS=" ";} { $$1= ""; print}' tmp.mem > $@
|
||||
rm tmp.mem
|
||||
|
||||
avr_progmem.hex : avr_progmem.out
|
||||
$(OBJCOPY) -R .eeprom -O ihex avr_progmem.out avr_progmem.hex
|
||||
avr_progmem.out : $(OBJECTS)
|
||||
$(CC) $(CFLAGS) -o avr_progmem.out -Wl,-Map,avr_progmem.map $^
|
||||
%.o : %.c
|
||||
$(CC) $(CFLAGS) -Os -c $<
|
||||
%.o : %.S
|
||||
$(CC) $(CFLAGS) -Os -c $<
|
||||
|
||||
.phony: clean
|
||||
|
||||
clean:
|
||||
rm -f avrz80cpu.bit avr_progmem.mem avr_progmem.hex avr_progmem.out avr_progmem.map *.o
|
@ -70,10 +70,12 @@ begin
|
||||
Addr => Addr,
|
||||
Data => (others => '0'),
|
||||
Phi2 => Phi2,
|
||||
RNW => RNW,
|
||||
Rd_n => not RNW,
|
||||
Wr_n => RNW,
|
||||
Sync => Sync,
|
||||
Rdy => Rdy,
|
||||
nRST => nRST,
|
||||
nRSTin => nRST,
|
||||
nRSTout => nRST,
|
||||
Regs => (others => '0'),
|
||||
RdOut => open,
|
||||
WrOut => open,
|
||||
@ -94,7 +96,9 @@ begin
|
||||
led8 => led8,
|
||||
tmosi => tmosi,
|
||||
tdin => tdin,
|
||||
tcclk => tcclk
|
||||
tcclk => tcclk,
|
||||
SS_Step => open,
|
||||
SS_Single => open
|
||||
);
|
||||
|
||||
end behavioral;
|
||||
|
@ -105,10 +105,12 @@ begin
|
||||
Addr => Addr_int,
|
||||
Data => Data,
|
||||
Phi2 => busmon_clk,
|
||||
RNW => R_W_n_int,
|
||||
Rd_n => not R_W_n_int,
|
||||
Wr_n => R_W_n_int,
|
||||
Sync => Sync_int,
|
||||
Rdy => Rdy_int,
|
||||
nRST => Res_n,
|
||||
nRSTin => Res_n,
|
||||
nRSTout => Res_n,
|
||||
trig => trig,
|
||||
lcd_rs => open,
|
||||
lcd_rw => open,
|
||||
@ -129,7 +131,9 @@ begin
|
||||
WrOut => memory_wr,
|
||||
AddrOut => memory_addr,
|
||||
DataOut => memory_dout,
|
||||
DataIn => memory_din
|
||||
DataIn => memory_din,
|
||||
SS_Step => open,
|
||||
SS_Single => open
|
||||
);
|
||||
|
||||
GenT65Core: if UseT65Core generate
|
||||
|
@ -35,10 +35,12 @@ entity BusMonCore is
|
||||
Addr : in std_logic_vector(15 downto 0);
|
||||
Data : in std_logic_vector(7 downto 0);
|
||||
Phi2 : in std_logic;
|
||||
RNW : in std_logic;
|
||||
Rd_n : in std_logic;
|
||||
Wr_n : in std_logic;
|
||||
Sync : in std_logic;
|
||||
Rdy : out std_logic;
|
||||
nRST : inout std_logic;
|
||||
nRSTin : in std_logic;
|
||||
nRSTout : out std_logic;
|
||||
|
||||
-- 6502 Registers
|
||||
-- unused in pure bus monitor mode
|
||||
@ -52,6 +54,10 @@ entity BusMonCore is
|
||||
DataOut : out std_logic_vector(7 downto 0);
|
||||
DataIn : in std_logic_vector(7 downto 0);
|
||||
|
||||
-- Single Step interface
|
||||
SS_Single : out std_logic;
|
||||
SS_Step : out std_logic;
|
||||
|
||||
-- External trigger inputs
|
||||
trig : in std_logic_vector(1 downto 0);
|
||||
|
||||
@ -334,7 +340,7 @@ begin
|
||||
status := "1001";
|
||||
end if;
|
||||
else
|
||||
if (RNW = '1') then
|
||||
if (Rd_n = '0') then
|
||||
if (reg_mode_bar = '1') then
|
||||
bactive := '1';
|
||||
status := "0010";
|
||||
@ -343,7 +349,8 @@ begin
|
||||
wactive := '1';
|
||||
status := "1010";
|
||||
end if;
|
||||
else
|
||||
end if;
|
||||
if (Wr_n = '0') then
|
||||
if (reg_mode_baw = '1') then
|
||||
bactive := '1';
|
||||
status := "0100";
|
||||
@ -381,7 +388,7 @@ begin
|
||||
if rising_edge(Phi2) then
|
||||
|
||||
-- Cycle counter, wraps every 16s at 1MHz
|
||||
if (nRST = '0') then
|
||||
if (nRSTin = '0') then
|
||||
cycleCount <= (others => '0');
|
||||
elsif (Rdy_int = '1') then
|
||||
cycleCount <= cycleCount + 1;
|
||||
@ -396,6 +403,7 @@ begin
|
||||
memory_rd <= '0';
|
||||
memory_wr <= '0';
|
||||
auto_inc <= '0';
|
||||
SS_Step <= '0';
|
||||
if (cmd_edge2 = '0' and cmd_edge1 = '1') then
|
||||
if (cmd(4 downto 1) = "0000") then
|
||||
single <= cmd(0);
|
||||
@ -449,15 +457,16 @@ begin
|
||||
|
||||
if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "01000")) then
|
||||
Rdy_int <= (not brkpt_active);
|
||||
SS_Step <= '1';
|
||||
else
|
||||
Rdy_int <= (not Sync);
|
||||
end if;
|
||||
|
||||
-- 6502 Reset needs to be open collector
|
||||
if (reset = '1') then
|
||||
nRST <= '0';
|
||||
nRSTout <= '0';
|
||||
else
|
||||
nRST <= 'Z';
|
||||
nRSTout <= 'Z';
|
||||
end if;
|
||||
|
||||
-- Latch instruction address for the whole cycle
|
||||
@ -494,6 +503,7 @@ begin
|
||||
WrOut <= memory_wr;
|
||||
AddrOut <= addr_dout_reg(23 downto 8);
|
||||
DataOut <= addr_dout_reg(7 downto 0);
|
||||
SS_Single <= single;
|
||||
|
||||
end behavioral;
|
||||
|
||||
|
1107
src/T80/T80.vhd
Normal file
1107
src/T80/T80.vhd
Normal file
File diff suppressed because it is too large
Load Diff
371
src/T80/T80_ALU.vhd
Normal file
371
src/T80/T80_ALU.vhd
Normal file
@ -0,0 +1,371 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_ALU;
|
||||
|
||||
architecture rtl of T80_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
|
||||
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
|
||||
process (Carry_v, Carry7_v, Q_v)
|
||||
begin
|
||||
if(Mode=2) then
|
||||
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
|
||||
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
end;
|
2024
src/T80/T80_MCode.vhd
Normal file
2024
src/T80/T80_MCode.vhd
Normal file
File diff suppressed because it is too large
Load Diff
229
src/T80/T80_Pack.vhd
Normal file
229
src/T80/T80_Pack.vhd
Normal file
@ -0,0 +1,229 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T80_Pack is
|
||||
|
||||
constant aNone : std_logic_vector(2 downto 0) := "111";
|
||||
constant aBC : std_logic_vector(2 downto 0) := "000";
|
||||
constant aDE : std_logic_vector(2 downto 0) := "001";
|
||||
constant aXY : std_logic_vector(2 downto 0) := "010";
|
||||
constant aIOA : std_logic_vector(2 downto 0) := "100";
|
||||
constant aSP : std_logic_vector(2 downto 0) := "101";
|
||||
constant aZI : std_logic_vector(2 downto 0) := "110";
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic;
|
||||
Regs : out std_logic_vector(63 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
XY_State : in std_logic_vector(1 downto 0);
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
XYbit_undoc : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
114
src/T80/T80_Reg.vhd
Normal file
114
src/T80/T80_Reg.vhd
Normal file
@ -0,0 +1,114 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
|
||||
end;
|
176
src/T80/T80_RegX.vhd
Normal file
176
src/T80/T80_RegX.vhd
Normal file
@ -0,0 +1,176 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- T80 Registers for Xilinx Select RAM
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Removed UNISIM library and added componet declaration
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
component RAM16X1D
|
||||
port(
|
||||
DPO : out std_ulogic;
|
||||
SPO : out std_ulogic;
|
||||
A0 : in std_ulogic;
|
||||
A1 : in std_ulogic;
|
||||
A2 : in std_ulogic;
|
||||
A3 : in std_ulogic;
|
||||
D : in std_ulogic;
|
||||
DPRA0 : in std_ulogic;
|
||||
DPRA1 : in std_ulogic;
|
||||
DPRA2 : in std_ulogic;
|
||||
DPRA3 : in std_ulogic;
|
||||
WCLK : in std_ulogic;
|
||||
WE : in std_ulogic);
|
||||
end component;
|
||||
|
||||
signal ENH : std_logic;
|
||||
signal ENL : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
ENH <= CEN and WEH;
|
||||
ENL <= CEN and WEL;
|
||||
|
||||
bG1: for I in 0 to 7 generate
|
||||
begin
|
||||
Reg1H : RAM16X1D
|
||||
port map(
|
||||
DPO => DOBH(i),
|
||||
SPO => DOAH(i),
|
||||
A0 => AddrA(0),
|
||||
A1 => AddrA(1),
|
||||
A2 => AddrA(2),
|
||||
A3 => '0',
|
||||
D => DIH(i),
|
||||
DPRA0 => AddrB(0),
|
||||
DPRA1 => AddrB(1),
|
||||
DPRA2 => AddrB(2),
|
||||
DPRA3 => '0',
|
||||
WCLK => Clk,
|
||||
WE => ENH);
|
||||
Reg1L : RAM16X1D
|
||||
port map(
|
||||
DPO => DOBL(i),
|
||||
SPO => DOAL(i),
|
||||
A0 => AddrA(0),
|
||||
A1 => AddrA(1),
|
||||
A2 => AddrA(2),
|
||||
A3 => '0',
|
||||
D => DIL(i),
|
||||
DPRA0 => AddrB(0),
|
||||
DPRA1 => AddrB(1),
|
||||
DPRA2 => AddrB(2),
|
||||
DPRA3 => '0',
|
||||
WCLK => Clk,
|
||||
WE => ENL);
|
||||
Reg2H : RAM16X1D
|
||||
port map(
|
||||
DPO => DOCH(i),
|
||||
SPO => open,
|
||||
A0 => AddrA(0),
|
||||
A1 => AddrA(1),
|
||||
A2 => AddrA(2),
|
||||
A3 => '0',
|
||||
D => DIH(i),
|
||||
DPRA0 => AddrC(0),
|
||||
DPRA1 => AddrC(1),
|
||||
DPRA2 => AddrC(2),
|
||||
DPRA3 => '0',
|
||||
WCLK => Clk,
|
||||
WE => ENH);
|
||||
Reg2L : RAM16X1D
|
||||
port map(
|
||||
DPO => DOCL(i),
|
||||
SPO => open,
|
||||
A0 => AddrA(0),
|
||||
A1 => AddrA(1),
|
||||
A2 => AddrA(2),
|
||||
A3 => '0',
|
||||
D => DIL(i),
|
||||
DPRA0 => AddrC(0),
|
||||
DPRA1 => AddrC(1),
|
||||
DPRA2 => AddrC(2),
|
||||
DPRA3 => '0',
|
||||
WCLK => Clk,
|
||||
WE => ENL);
|
||||
end generate;
|
||||
|
||||
end;
|
286
src/T80/T80a.vhd
Normal file
286
src/T80/T80a.vhd
Normal file
@ -0,0 +1,286 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core, asynchronous top level
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0208 : First complete release
|
||||
--
|
||||
-- 0211 : Fixed interrupt cycle
|
||||
--
|
||||
-- 0235 : Updated for T80 interface change
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0240 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
-- 0247 : Fixed bus req/ack cycle
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80a is
|
||||
generic(
|
||||
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
);
|
||||
port(
|
||||
-- Additions
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
WAIT_s_out : out std_logic;
|
||||
Regs : out std_logic_vector(63 downto 0);
|
||||
Write_out : out std_logic;
|
||||
-- Original Signals
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
D : inout std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80a;
|
||||
|
||||
architecture rtl of T80a is
|
||||
|
||||
signal CEN : std_logic;
|
||||
signal Reset_s : std_logic;
|
||||
signal IntCycle_n : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal MREQ : std_logic;
|
||||
signal MReq_Inhibit : std_logic;
|
||||
signal Req_Inhibit : std_logic;
|
||||
signal RD : std_logic;
|
||||
signal MREQ_n_i : std_logic;
|
||||
signal IORQ_n_i : std_logic;
|
||||
signal RD_n_i : std_logic;
|
||||
signal WR_n_i : std_logic;
|
||||
signal RFSH_n_i : std_logic;
|
||||
signal BUSAK_n_i : std_logic;
|
||||
signal A_i : std_logic_vector(15 downto 0);
|
||||
signal DO : std_logic_vector(7 downto 0);
|
||||
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
|
||||
signal Wait_s : std_logic;
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
CEN <= '1';
|
||||
|
||||
BUSAK_n <= BUSAK_n_i;
|
||||
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
|
||||
RD_n_i <= not RD or Req_Inhibit;
|
||||
|
||||
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
|
||||
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
|
||||
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
Reset_s <= '0';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
Reset_s <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => Mode,
|
||||
IOWait => 1)
|
||||
port map(
|
||||
CEN => CEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n_i,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_s,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => Reset_s,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n_i,
|
||||
CLK_n => CLK_n,
|
||||
A => A_i,
|
||||
DInst => D,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n,
|
||||
Regs => Regs
|
||||
);
|
||||
|
||||
|
||||
process (CLK_n)
|
||||
begin
|
||||
if CLK_n'event and CLK_n = '0' then
|
||||
Wait_s <= WAIT_n;
|
||||
if TState = "011" and BUSAK_n_i = '1' then
|
||||
DI_Reg <= to_x01(D);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
WR_n_i <= '1';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
WR_n_i <= '1';
|
||||
if TState = "001" or (TState = "010" and Wait_s = '0') then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
|
||||
WR_n_i <= not Write;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- process (Reset_s,CLK_n)
|
||||
-- begin
|
||||
-- if Reset_s = '0' then
|
||||
-- WR_n_i <= '1';
|
||||
-- elsif CLK_n'event and CLK_n = '0' then
|
||||
-- WR_n_i <= '1';
|
||||
-- if TState = "010" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
|
||||
-- WR_n_i <= not Write;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process (Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
Req_Inhibit <= '0';
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if MCycle = "001" and TState = "010" then
|
||||
Req_Inhibit <= '1';
|
||||
else
|
||||
Req_Inhibit <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
MReq_Inhibit <= '0';
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
if MCycle = "001" and TState = "010" then
|
||||
MReq_Inhibit <= '1';
|
||||
else
|
||||
MReq_Inhibit <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(Reset_s,CLK_n)
|
||||
begin
|
||||
if Reset_s = '0' then
|
||||
RD <= '0';
|
||||
IORQ_n_i <= '1';
|
||||
MREQ <= '0';
|
||||
elsif CLK_n'event and CLK_n = '0' then
|
||||
|
||||
if MCycle = "001" then
|
||||
if TState = "001" then
|
||||
RD <= IntCycle_n;
|
||||
MREQ <= IntCycle_n;
|
||||
IORQ_n_i <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
RD <= '0';
|
||||
IORQ_n_i <= '1';
|
||||
MREQ <= '1';
|
||||
end if;
|
||||
if TState = "100" then
|
||||
MREQ <= '0';
|
||||
end if;
|
||||
else
|
||||
if TState = "001" and NoRead = '0' then
|
||||
RD <= not Write;
|
||||
IORQ_n_i <= not IORQ;
|
||||
MREQ <= not IORQ;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
RD <= '0';
|
||||
IORQ_n_i <= '1';
|
||||
MREQ <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
TS <= TState;
|
||||
WAIT_s_out <= WAIT_s;
|
||||
Write_out <= Write;
|
||||
end;
|
38
src/Z80CpuMon.bmm
Normal file
38
src/Z80CpuMon.bmm
Normal file
@ -0,0 +1,38 @@
|
||||
ADDRESS_MAP avrmap PPC405 0
|
||||
|
||||
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
BUS_BLOCK
|
||||
mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
|
||||
END_BUS_BLOCK;
|
||||
|
||||
END_ADDRESS_SPACE;
|
||||
|
||||
END_ADDRESS_MAP;
|
83
src/Z80CpuMon.ucf
Normal file
83
src/Z80CpuMon.ucf
Normal file
@ -0,0 +1,83 @@
|
||||
|
||||
NET "CLK_n" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 | PERIOD = 20.35ns ; # 49.152 MHz Oscillator
|
||||
|
||||
NET "Addr<11>" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 1
|
||||
NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 2
|
||||
NET "Addr<13>" LOC="P18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 3
|
||||
NET "Addr<14>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 4
|
||||
NET "Addr<15>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 5
|
||||
NET "CLK_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PERIOD = 250.0 ; # Z80 pin 6
|
||||
NET "Data<4>" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 7
|
||||
NET "Data<3>" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 8
|
||||
NET "Data<5>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 9
|
||||
NET "Data<6>" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 10
|
||||
#NET "VCC" LOC="P40" | IOSTANDARD = LVCMOS33 ; # Z80 pin 11
|
||||
NET "Data<2>" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 12
|
||||
NET "Data<7>" LOC="P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 13
|
||||
NET "Data<0>" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 14
|
||||
NET "Data<1>" LOC="P53" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 15
|
||||
NET "INT_n" LOC="P54" | IOSTANDARD = LVCMOS33 ; # Z80 pin 16
|
||||
NET "NMI_n" LOC="P57" | IOSTANDARD = LVCMOS33 ; # Z80 pin 17
|
||||
NET "HALT_n" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 18
|
||||
NET "MREQ_n" LOC="P60" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 19
|
||||
NET "IORQ_n" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 20
|
||||
NET "RD_n" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 21
|
||||
NET "WR_n" LOC="P68" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 22
|
||||
NET "BUSAK_n" LOC="P70" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 23
|
||||
NET "WAIT_n" LOC="P71" | IOSTANDARD = LVCMOS33 ; # Z80 pin 24
|
||||
NET "BUSRQ_n" LOC="P86" | IOSTANDARD = LVCMOS33 ; # Z80 pin 25
|
||||
NET "RESET_n" LOC="P84" | IOSTANDARD = LVCMOS33 ; # Z80 pin 26
|
||||
NET "M1_n" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 27
|
||||
NET "RFSH_n" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 28
|
||||
#NET "GND" LOC="P79" | IOSTANDARD = LVCMOS33 ; # Z80 pin 29
|
||||
NET "Addr<0>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 30
|
||||
NET "Addr<1>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 31
|
||||
NET "Addr<2>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 32
|
||||
NET "Addr<3>" LOC="P3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 33
|
||||
NET "Addr<4>" LOC="P2" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 34
|
||||
NET "Addr<5>" LOC="P4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 35
|
||||
NET "Addr<6>" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 36
|
||||
NET "Addr<7>" LOC="P90" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 37
|
||||
NET "Addr<8>" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 38
|
||||
NET "Addr<9>" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 39
|
||||
NET "Addr<10>" LOC="P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ; # Z80 pin 40
|
||||
|
||||
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
|
||||
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
|
||||
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
|
||||
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
|
||||
NET "nsw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
|
||||
|
||||
# I/O's for test connector
|
||||
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ;
|
||||
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ;
|
||||
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ;
|
||||
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
|
||||
|
||||
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
|
||||
|
||||
NET "test1" LOC="P65" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ;
|
||||
NET "test2" LOC="P66" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ;
|
||||
NET "test3" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ;
|
||||
NET "test4" LOC="P91" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 2 ;
|
||||
|
||||
|
||||
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
|
||||
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
|
||||
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
|
||||
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
|
||||
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
|
||||
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
|
||||
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
|
||||
|
||||
|
||||
|
266
src/Z80CpuMon.vhd
Normal file
266
src/Z80CpuMon.vhd
Normal file
@ -0,0 +1,266 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Copyright (c) 2015 David Banks
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- ____ ____
|
||||
-- / /\/ /
|
||||
-- /___/ \ /
|
||||
-- \ \ \/
|
||||
-- \ \
|
||||
-- / / Filename : Z80CpuMon.vhd
|
||||
-- /___/ /\ Timestamp : 22/06/2015
|
||||
-- \ \ / \
|
||||
-- \___\/\___\
|
||||
--
|
||||
--Design Name: Z80CpuMon
|
||||
--Device: XC3S250E
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
use work.OhoPack.all ;
|
||||
|
||||
entity Z80CpuMon is
|
||||
generic (
|
||||
UseT80Core : boolean := true
|
||||
);
|
||||
port (
|
||||
clock49 : in std_logic;
|
||||
|
||||
-- Z80 Signals
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
Addr : out std_logic_vector(15 downto 0);
|
||||
Data : inout std_logic_vector(7 downto 0);
|
||||
|
||||
-- External trigger inputs
|
||||
trig : in std_logic_vector(1 downto 0);
|
||||
|
||||
-- Serial Console
|
||||
avr_RxD : in std_logic;
|
||||
avr_TxD : out std_logic;
|
||||
|
||||
-- GODIL Switches
|
||||
sw1 : in std_logic;
|
||||
nsw2 : in std_logic;
|
||||
|
||||
-- GODIL LEDs
|
||||
led3 : out std_logic;
|
||||
led6 : out std_logic;
|
||||
led8 : out std_logic;
|
||||
|
||||
-- OHO_DY1 connected to test connector
|
||||
tmosi : out std_logic;
|
||||
tdin : out std_logic;
|
||||
tcclk : out std_logic;
|
||||
|
||||
-- Debugging signals
|
||||
test1 : out std_logic;
|
||||
test2 : out std_logic;
|
||||
test3 : out std_logic;
|
||||
test4 : out std_logic
|
||||
|
||||
);
|
||||
end Z80CpuMon;
|
||||
|
||||
architecture behavioral of Z80CpuMon is
|
||||
|
||||
signal RESET_n_int : std_logic;
|
||||
signal cpu_clk : std_logic;
|
||||
signal busmon_clk : std_logic;
|
||||
|
||||
signal Addr_int : std_logic_vector(15 downto 0);
|
||||
signal RD_n_int : std_logic;
|
||||
signal WR_n_int : std_logic;
|
||||
signal MREQ_n_int : std_logic;
|
||||
signal IORQ_n_int : std_logic;
|
||||
signal M1_n_int : std_logic;
|
||||
signal WAIT_n_int : std_logic;
|
||||
signal WAIT_s : std_logic;
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
signal SS_Single : std_logic;
|
||||
signal SS_Step : std_logic;
|
||||
signal SS_Step_held : std_logic;
|
||||
|
||||
signal Regs : std_logic_vector(63 downto 0);
|
||||
signal Write : std_logic;
|
||||
|
||||
signal INT_n_sync : std_logic;
|
||||
signal NMI_n_sync : std_logic;
|
||||
|
||||
signal Rdy : std_logic;
|
||||
signal Read_n : std_logic;
|
||||
signal Read_n0 : std_logic;
|
||||
signal Read_n1 : std_logic;
|
||||
signal Write_n : std_logic;
|
||||
signal Write_n0 : std_logic;
|
||||
signal Sync : std_logic;
|
||||
signal Sync0 : std_logic;
|
||||
signal nRST : std_logic;
|
||||
|
||||
signal ex_data : std_logic_vector(7 downto 0);
|
||||
signal rd_data : std_logic_vector(7 downto 0);
|
||||
signal mon_data : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
mon : entity work.BusMonCore
|
||||
generic map (
|
||||
num_comparators => 1
|
||||
)
|
||||
port map (
|
||||
clock49 => clock49,
|
||||
Addr => Addr_int,
|
||||
Data => mon_data,
|
||||
Phi2 => busmon_clk,
|
||||
Rd_n => Read_n,
|
||||
Wr_n => Write_n,
|
||||
Sync => Sync,
|
||||
Rdy => Rdy,
|
||||
SS_Single => SS_Single,
|
||||
SS_Step => SS_Step,
|
||||
nRSTin => RESET_n_int,
|
||||
nRSTout => nRST,
|
||||
trig => trig,
|
||||
lcd_rs => open,
|
||||
lcd_rw => open,
|
||||
lcd_e => open,
|
||||
lcd_db => open,
|
||||
avr_RxD => avr_RxD,
|
||||
avr_TxD => avr_TxD,
|
||||
sw1 => '0',
|
||||
nsw2 => nsw2,
|
||||
led3 => led3,
|
||||
led6 => led6,
|
||||
led8 => led8,
|
||||
tmosi => tmosi,
|
||||
tdin => tdin,
|
||||
tcclk => tcclk,
|
||||
Regs => Regs(63 downto 0),
|
||||
RdOut => open,
|
||||
WrOut => open,
|
||||
AddrOut => open,
|
||||
DataOut => open,
|
||||
DataIn => (others => '0')
|
||||
);
|
||||
|
||||
GenT80Core: if UseT80Core generate
|
||||
inst_t80: entity work.T80a port map (
|
||||
TS => TState,
|
||||
WAIT_s_out => WAIT_s,
|
||||
Regs => Regs,
|
||||
Write_out => Write,
|
||||
RESET_n => RESET_n_int,
|
||||
CLK_n => cpu_clk,
|
||||
WAIT_n => WAIT_n_int,
|
||||
INT_n => INT_n_sync,
|
||||
NMI_n => NMI_n_sync,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
M1_n => M1_n_int,
|
||||
MREQ_n => MREQ_n_int,
|
||||
IORQ_n => IORQ_n_int,
|
||||
RD_n => RD_n_int,
|
||||
WR_n => WR_n_int,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
A => Addr_int,
|
||||
D => Data
|
||||
);
|
||||
end generate;
|
||||
|
||||
WAIT_n_int <= WAIT_n when SS_Single = '0'
|
||||
else WAIT_n and SS_Step_held;
|
||||
|
||||
|
||||
sync_gen : process(CLK_n, RESET_n_int)
|
||||
begin
|
||||
if RESET_n_int = '0' then
|
||||
NMI_n_sync <= '1';
|
||||
INT_n_sync <= '1';
|
||||
SS_Step_held <= '1';
|
||||
elsif rising_edge(CLK_n) then
|
||||
NMI_n_sync <= NMI_n;
|
||||
INT_n_sync <= INT_n;
|
||||
if (M1_n_int = '0' and TState = "001") then
|
||||
-- stop at the end of T1 instruction fetch
|
||||
SS_Step_held <= '0';
|
||||
elsif (SS_Step = '1') then
|
||||
-- start again when the single step command is issues
|
||||
SS_Step_held <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Make the monitoring decision in the middle of T2, but only if WAIT_n is '1'
|
||||
Sync0 <= (WAIT_n_int and (not Write) and (not MREQ_n_int) and (not M1_n_int)) when TState = "010" else '0';
|
||||
Read_n0 <= not (WAIT_n_int and (not Write) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
|
||||
Write_n0 <= not (WAIT_n_int and ( Write) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
|
||||
|
||||
-- Hold the monitoring decision so it is valid on the rising edge of the clock
|
||||
-- For instruction fetches and writes, the monitor sees these at the start of T3
|
||||
-- For reads, the data can arrive in the middle of T3 so delay until end of T3
|
||||
watch_gen : process(CLK_n)
|
||||
begin
|
||||
if falling_edge(CLK_n) then
|
||||
Sync <= Sync0;
|
||||
Read_n1 <= Read_n0;
|
||||
Read_n <= Read_n1;
|
||||
Write_n <= Write_n0;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Register the exec/write data on the rising at the end of T2
|
||||
ex_data_latch : process(CLK_n)
|
||||
begin
|
||||
if rising_edge(CLK_n) then
|
||||
if (Sync = '1' or Write_n = '0') then
|
||||
ex_data <= Data;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Register the read data on the falling edge of clock in the middle of T3
|
||||
rd_data_latch : process(CLK_n)
|
||||
begin
|
||||
if falling_edge(CLK_n) then
|
||||
if (Read_n1 = '0') then
|
||||
rd_data <= Data;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Mux the data seen by the bus monitor appropriately
|
||||
mon_data <= rd_data when Read_n <= '0' else ex_data;
|
||||
|
||||
Addr <= Addr_int;
|
||||
WR_n <= WR_n_int;
|
||||
RD_n <= RD_n_int;
|
||||
MREQ_n <= MREQ_n_int;
|
||||
IORQ_n <= IORQ_n_int;
|
||||
M1_n <= M1_n_int;
|
||||
RESET_n_int <= RESET_n and (not sw1) and nRST;
|
||||
|
||||
test1 <= TState(0);
|
||||
test2 <= TState(1);
|
||||
test3 <= TState(2);
|
||||
test4 <= CLK_n;
|
||||
|
||||
cpu_clk <= CLK_n;
|
||||
busmon_clk <= CLK_n;
|
||||
|
||||
end behavioral;
|
Loading…
Reference in New Issue
Block a user