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Added option to do repeat a read/write command n times (where n can be large), incremented version to 0.37

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Change-Id: I4b1b02e8d67a581acbf4d5b044e86ffb2bc7e27e
This commit is contained in:
David Banks 2015-06-22 18:11:11 +01:00
parent 3c7fb3429e
commit eec6e10440
3 changed files with 75 additions and 52 deletions
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BIN
AtomCpuMon.bit
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71
firmware/AtomBusMon.c
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@ -258,12 +258,14 @@ unsigned char dopaddr[256] =
#define CMD_WATCH_READ 0x09
#define CMD_FIFO_RST 0x0A
#define CMD_LOAD_MEM 0x0C
#define CMD_RD_MEM 0x0E
#define CMD_WR_MEM 0x0F
#define CMD_RD_MEM 0x10
#define CMD_RD_MEM_INC 0x11
#define CMD_WR_MEM 0x12
#define CMD_WR_MEM_INC 0x13
// Control bits
#define CMD_MASK 0x1F
#define CMD_EDGE 0x10
#define CMD_MASK 0x3F
#define CMD_EDGE 0x20
#define MUXSEL_MASK 0x1F
#define MUXSEL_BIT 0
@ -328,7 +330,7 @@ char *triggerStrings[NUM_TRIGGERS] = {
};
#define VERSION "0.36"
#define VERSION "0.37"
#ifdef EMBEDDED_6502
#define NUM_CMDS 27
@ -649,29 +651,27 @@ unsigned int readByte() {
return hwRead8(OFFSET_DATA);
}
unsigned int readByteInc() {
hwCmd(CMD_RD_MEM_INC, 0);
Delay_us(10);
return hwRead8(OFFSET_DATA);
}
void writeByte() {
hwCmd(CMD_WR_MEM, 0);
}
unsigned int readMem(unsigned int addr) {
loadAddr(addr);
return readByte();
void writeByteInc() {
hwCmd(CMD_WR_MEM_INC, 0);
}
void writeMem(unsigned int addr, unsigned int data) {
loadData(data);
loadAddr(addr);
writeByte();
}
unsigned int disassemble(unsigned int addr)
{
unsigned int temp;
unsigned int op = readByte();
unsigned int op = readByteInc();
int mode = dopaddr[op];
unsigned int p1 = (mode > MARK2) ? readByte() : 0;
unsigned int p2 = (mode > MARK3) ? readByte() : 0;
unsigned int p1 = (mode > MARK2) ? readByteInc() : 0;
unsigned int p2 = (mode > MARK3) ? readByteInc() : 0;
log0("%04X : %s ", addr, opStrings[dopname[op]]);
switch (mode)
@ -840,7 +840,7 @@ void doCmdMem(char *params) {
loadAddr(memAddr);
for (i = 0; i < 0x100; i+= 16) {
for (j = 0; j < 16; j++) {
row[j] = readByte();
row[j] = readByteInc();
}
log0("%04X ", memAddr + i);
for (j = 0; j < 16; j++) {
@ -871,17 +871,32 @@ void doCmdDis(char *params) {
void doCmdWrite(char *params) {
unsigned int addr;
unsigned int data;
sscanf(params, "%x %x", &addr, &data);
long count = 1;
sscanf(params, "%x %x %ld", &addr, &data, &count);
log0("Wr: %04X = %X\n", addr, data);
writeMem(addr, data);
loadData(data);
loadAddr(addr);
while (count-- > 0) {
writeByte();
}
}
void doCmdRead(char *params) {
unsigned int addr;
sscanf(params, "%x", &addr);
unsigned int data;
data = readMem(addr);
unsigned int data2;
long count = 1;
sscanf(params, "%x %ld", &addr, &count);
loadAddr(addr);
data = readByte();
log0("Rd: %04X = %X\n", addr, data);
while (count-- > 1) {
data2 = readByte();
if (data2 != data) {
log0("Inconsistent Rd: %02X <> %02X\n", data2, data);
}
data = data2;
}
}
void doCmdFill(char *params) {
@ -894,7 +909,7 @@ void doCmdFill(char *params) {
loadData(data);
loadAddr(start);
for (i = start; i <= end; i++) {
hwCmd(CMD_WR_MEM, 0);
writeByteInc();
}
}
@ -908,7 +923,7 @@ void doCmdCrc(char *params) {
sscanf(params, "%x %x", &start, &end);
loadAddr(start);
for (i = start; i <= end; i++) {
data = readByte();
data = readByteInc();
for (j = 0; j < 8; j++) {
crc = crc << 1;
crc = crc | (data & 1);
@ -951,13 +966,15 @@ void test(unsigned int start, unsigned int end, int data) {
// Write
srand(data);
for (i = start; i <= end; i++) {
writeMem(i, getData(i, data));
loadData(getData(i, data));
loadAddr(i);
writeByteInc();
}
// Read
srand(data);
loadAddr(start);
for (i = start; i <= end; i++) {
actual = readByte();
actual = readByteInc();
expected = getData(i, data);
if (expected != actual) {
log0("Fail at %04lX (Wrote: %02X, Read back %02X)\n", i, expected, actual);

56
src/BusMonCore.vhd
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@ -96,7 +96,7 @@ architecture behavioral of BusMonCore is
signal cmd_edge : std_logic;
signal cmd_edge1 : std_logic;
signal cmd_edge2 : std_logic;
signal cmd : std_logic_vector(3 downto 0);
signal cmd : std_logic_vector(4 downto 0);
signal addr_sync : std_logic_vector(15 downto 0);
signal addr_inst : std_logic_vector(15 downto 0);
@ -113,6 +113,7 @@ architecture behavioral of BusMonCore is
signal bw_status : std_logic_vector(3 downto 0);
signal bw_status1 : std_logic_vector(3 downto 0);
signal auto_inc : std_logic;
signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
signal brkpt_enable : std_logic;
@ -194,8 +195,8 @@ begin
portbout(1) => cmd(1),
portbout(2) => cmd(2),
portbout(3) => cmd(3),
portbout(4) => cmd_edge,
portbout(5) => open,
portbout(4) => cmd(4),
portbout(5) => cmd_edge,
portbout(6) => open,
portbout(7) => open,
@ -362,17 +363,19 @@ begin
end process;
-- 6502 Control Commands
-- 000x Enable/Disable single stepping
-- 001x Enable/Disable breakpoints / watches
-- 010x Load breakpoint register
-- 011x Reset
-- 1000 Single Step
-- 1001 FIFO Read
-- 1010 FIFO Reset
-- 110x Load memory address/data register
-- 1110 Read memory
-- 1111 Write memory
-- 0000x Enable/Disable single stepping
-- 0001x Enable/Disable breakpoints / watches
-- 0010x Load breakpoint register
-- 0011x Reset
-- 01000 Single Step
-- 01001 FIFO Read
-- 01010 FIFO Reset
-- 0110x Load memory address/data register
-- 0111x Unused
-- 1000x Read memory
-- 1001x Write memory
-- 101xx Unused
-- 11xxx Unused
risingProcess: process (Phi2)
begin
if rising_edge(Phi2) then
@ -392,47 +395,50 @@ begin
fifo_rst <= '0';
memory_rd <= '0';
memory_wr <= '0';
auto_inc <= '0';
if (cmd_edge2 = '0' and cmd_edge1 = '1') then
if (cmd(3 downto 1) = "000") then
if (cmd(4 downto 1) = "0000") then
single <= cmd(0);
end if;
if (cmd(3 downto 1) = "001") then
if (cmd(4 downto 1) = "0001") then
brkpt_enable <= cmd(0);
end if;
if (cmd(3 downto 1) = "010") then
if (cmd(4 downto 1) = "0010") then
brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
end if;
if (cmd(3 downto 1) = "110") then
if (cmd(4 downto 1) = "0110") then
addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
end if;
if (cmd(3 downto 1) = "011") then
if (cmd(4 downto 1) = "0011") then
reset <= cmd(0);
end if;
if (cmd(3 downto 0) = "1001") then
if (cmd(4 downto 0) = "01001") then
fifo_rd <= '1';
end if;
if (cmd(3 downto 0) = "1010") then
if (cmd(4 downto 0) = "01010") then
fifo_rst <= '1';
end if;
if (cmd(3 downto 0) = "1110") then
if (cmd(4 downto 1) = "1000") then
memory_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(3 downto 0) = "1111") then
if (cmd(4 downto 1) = "1001") then
memory_wr <= '1';
auto_inc <= cmd(0);
end if;
end if;
-- Auto increment the memory address reg the cycle after a rd/wr
if (memory_rd = '1' or memory_wr = '1') then
if (auto_inc = '1' and (memory_rd = '1' or memory_wr = '1')) then
addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1;
end if;
@ -441,7 +447,7 @@ begin
single <= '1';
end if;
if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "1000")) then
if ((single = '0') or (cmd_edge2 = '0' and cmd_edge1 = '1' and cmd = "01000")) then
Rdy_int <= (not brkpt_active);
else
Rdy_int <= (not Sync);