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Updated lx9_dave/ice6502 for active level shifter design
Change-Id: Ib2e98050d02c9c1e3dd7c9a9b63eea118b95a540
This commit is contained in:
David Banks
parent
a25a008ffc
commit
c660ea87be
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@ -1,5 +1,5 @@
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--------------------------------------------------------------------------------
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-- Copyright (c) 2018 David Banks
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-- Copyright (c) 2019 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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@ -8,11 +8,11 @@
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-- \ \ \/
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-- \ \
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-- / / Filename : W65C02CpuMon.vhd
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-- /___/ /\ Timestamp : 20/11/2018
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-- /___/ /\ Timestamp : 20/09/2019
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: W65C02BusMon
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--Design Name: W65C02CpuMon
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--Device: XC6SLX9
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--
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--
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@ -20,6 +20,7 @@
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-- OEAH_n
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-- OEAL_n
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-- OED_n
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-- DIRD
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-- BE
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-- ML_n
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-- VP_n
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@ -31,28 +32,28 @@ use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity W65C02CpuMon is
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generic (
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generic (
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UseT65Core : boolean := true;
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UseAlanDCore : boolean := false;
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LEDsActiveHigh : boolean := true; -- default value for EEPIZZA
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SW1ActiveHigh : boolean := true; -- default value for EEPIZZA
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SW2ActiveHigh : boolean := true; -- default value for EEPIZZA
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ClkMult : integer := 10; -- default value for EEPIZZA
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ClkDiv : integer := 31; -- default value for EEPIZZA
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ClkPer : real := 20.000 -- default value for EEPIZZA
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SW1ActiveHigh : boolean := false; -- default value for EEPIZZA
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SW2ActiveHigh : boolean := false; -- default value for EEPIZZA
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ClkMult : integer := 8; -- default value for EEPIZZA
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ClkDiv : integer := 25; -- default value for EEPIZZA
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ClkPer : real := 16.000 -- default value for EEPIZZA
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);
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port (
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clock49 : in std_logic;
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clock : in std_logic;
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-- 6502 Signals
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Phi0 : in std_logic;
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Phi1 : out std_logic;
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Phi2 : out std_logic;
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PhiIn : in std_logic;
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Phi1Out : out std_logic;
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Phi2Out : out std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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Sync : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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R_W_n : out std_logic;
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R_W_n : out std_logic_vector(1 downto 0);
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Data : inout std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n : inout std_logic;
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@ -64,15 +65,18 @@ entity W65C02CpuMon is
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VP_n : out std_logic;
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-- Level Shifter Controls
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OERW_n : out std_logic;
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OEAH_n : out std_logic;
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OEAL_n : out std_logic;
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OED_n : out std_logic;
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DIRD : out std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Jumpers
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fakeTube_n : in std_logic;
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-- ID/mode inputs
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mode : in std_logic;
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id : in std_logic_vector(3 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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@ -83,9 +87,9 @@ entity W65C02CpuMon is
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sw2 : in std_logic;
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-- LEDs
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led1 : out std_logic;
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led2 : out std_logic;
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 LED display
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tmosi : out std_logic;
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@ -112,12 +116,12 @@ begin
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ClkPer => ClkPer
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)
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port map (
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clock49 => clock49,
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clock49 => clock,
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-- 6502 Signals
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Phi0 => Phi0,
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Phi1 => Phi1,
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Phi2 => Phi2,
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Phi0 => PhiIn,
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Phi1 => Phi1Out,
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Phi2 => Phi2Out,
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IRQ_n => IRQ_n,
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NMI_n => NMI_n,
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Sync => Sync,
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@ -132,7 +136,7 @@ begin
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trig => trig,
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-- Jumpers
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fakeTube_n => fakeTube_n,
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fakeTube_n => '1',
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-- Serial Console
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avr_RxD => avr_RxD,
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@ -143,9 +147,9 @@ begin
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sw2 => sw2,
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-- LEDs
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led3 => led3,
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led6 => led6,
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led8 => led8,
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led3 => led2, -- trig 0
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led6 => led3, -- trig 1
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led8 => led1, -- break
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-- OHO_DY1 LED display
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tmosi => tmosi,
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@ -154,15 +158,17 @@ begin
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);
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-- 6502 Outputs
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R_W_n <= R_W_n_int;
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R_W_n <= R_W_n_int & R_W_n_int;
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-- 65C02 Outputs
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ML_n <= '1';
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VP_n <= '1';
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-- Level Shifter Controls
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OERW_n <= not (BE);
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OEAH_n <= not (BE);
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OEAL_n <= not (BE);
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OED_n <= not (BE or (Phi0 and not R_W_n_int)); -- TODO: might need to use a slightly delayed version of Phi0 here
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OED_n <= not (BE and PhiIn); -- TODO: might need to use a slightly delayed version of Phi2 here
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DIRD <= R_W_n_int;
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end behavioral;
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@ -1,16 +1,16 @@
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NET "clock49" TNM_NET = clk_period_grp_49;
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TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.00ns HIGH;
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NET "clock" TNM_NET = clk_period_grp_50;
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TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
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NET "Phi0" TNM_NET = clk_period_grp_phi0;
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TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 250ns LOW;
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NET "PhiIn" TNM_NET = clk_period_grp_phi;
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TIMESPEC TS_clk_period_phi = PERIOD "clk_period_grp_phi" 250ns LOW;
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NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "PhiIn" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "clock49" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
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NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
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NET "VP_n" LOC="P35" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
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#NET "Rdy" LOC="P79" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
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NET "Phi1" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
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NET "Phi1Out" LOC="P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
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NET "IRQ_n" LOC="P81" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
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NET "ML_n" LOC="P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
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NET "NMI_n" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
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@ -42,41 +42,54 @@ NET "Data<3>" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; #
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NET "Data<2>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
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NET "Data<1>" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
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NET "Data<0>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
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NET "R_W_n" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
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NET "R_W_n<0>" LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
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NET "R_W_n<1>" LOC="P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
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#NET "NC" LOC="P" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
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NET "BE" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
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NET "Phi0" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
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NET "PhiIn" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
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NET "SO_n" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
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NET "Phi2" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
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NET "Phi2Out" LOC="P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
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NET "Res_n" LOC="P74" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
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# Level-shifter OE signals
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NET "OEAL_n" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# Output Enables
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NET "OERW_n" LOC="P114" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "OEAH_n" LOC="P139" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "OEAL_n" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "OED_n" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "DIRD" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# LEDs and Switches
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NET "led3" LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
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NET "led6" LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
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NET "led8" LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
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NET "sw1" LOC="P132" | IOSTANDARD = LVCMOS33 ; # reset
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NET "sw2" LOC="P131" | IOSTANDARD = LVCMOS33 ; # interrupt
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NET "led1" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
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NET "led2" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
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NET "led3" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
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NET "sw1" LOC="P45" | IOSTANDARD = LVCMOS33 ; # reset
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NET "sw2" LOC="P66" | IOSTANDARD = LVCMOS33 ; # interrupt
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# 7-segment LED
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NET tmosi LOC="P45" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# ID/Jumper
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NET "mode" LOC="P140" | IOSTANDARD = LVCMOS33 ; # mode jumper
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NET "id<0>" LOC="P88 " | IOSTANDARD = LVCMOS33 ; # id links
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NET "id<1>" LOC="P87 " | IOSTANDARD = LVCMOS33 ; # id links
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NET "id<2>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # id links
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NET "id<3>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # id links
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# UART
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NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
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# External trigger inputs
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NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;
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NET "trig<1>" LOC="P127" | IOSTANDARD = LVCMOS33 ;
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NET "trig<0>" LOC="P127" | IOSTANDARD = LVCMOS33 ;
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NET "trig<1>" LOC="P126" | IOSTANDARD = LVCMOS33 ;
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# Jumpers
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NET "fakeTube_n" LOC="P123" | IOSTANDARD = LVCMOS33 ;
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# 7-segment LED (connect to J5 on FPGA board)
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NET "tmosi" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "tdin" LOC="P61" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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NET "tcclk" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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# Test outputs (connect to J5 on FPGA board)
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#NET "test1" LOC="P46" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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#NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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#NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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#NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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