6502: seperate top level for GODIL and old LX9, rename modules for consistency

Change-Id: I6d9f390a24b63a303f4a557e49ee68109af4c76a
This commit is contained in:
David Banks 2019-11-02 17:31:10 +00:00
parent cfce5b1bd7
commit c6f860ed2c
44 changed files with 3736 additions and 524 deletions

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@ -1,5 +1,5 @@
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
-------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
@ -7,34 +7,31 @@
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomBusMon.vhd
-- /___/ /\ Timestamp : 30/05/2015
-- / / Filename : MOS6502CpuMon.vhd
-- /___/ /\ Timestamp : 03/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomBusMon
--Device: XC3S250E
--Design Name: MOS6502CpuMon
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.OhoPack.all ;
entity AtomCpuMon is
entity MOS6502CpuMon is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false;
LEDsActiveHigh : boolean := false; -- default value correct for GODIL
SW1ActiveHigh : boolean := true; -- default value correct for GODIL
SW2ActiveHigh : boolean := false; -- default value correct for GODIL
ClkMult : integer := 10; -- default value correct for GODIL
ClkDiv : integer := 31; -- default value correct for GODIL
ClkPer : real := 20.345 -- default value correct for GODIL
UseT65Core : boolean;
UseAlanDCore : boolean;
ClkMult : integer;
ClkDiv : integer;
ClkPer : real;
num_comparators : integer;
avr_prog_mem_size : integer
);
port (
clock49 : in std_logic;
clock : in std_logic;
-- 6502 Signals
Phi0 : in std_logic;
@ -60,23 +57,23 @@ entity AtomCpuMon is
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- GODIL Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- Switches
sw_interrupt : in std_logic;
sw_reset : in std_logic;
-- GODIL LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end AtomCpuMon;
end MOS6502CpuMon;
architecture behavioral of AtomCpuMon is
architecture behavioral of MOS6502CpuMon is
signal clock_avr : std_logic;
@ -101,21 +98,8 @@ architecture behavioral of AtomCpuMon is
signal Res_n_in : std_logic;
signal Res_n_out : std_logic;
signal led3_n : std_logic; -- led to indicate ext trig 0 is active
signal led6_n : std_logic; -- led to indicate ext trig 1 is active
signal led8_n : std_logic; -- led to indicate CPU has hit a breakpoint (and is stopped)
signal sw_interrupt_n : std_logic; -- switch to pause the CPU
signal sw_reset_n : std_logic; -- switch to reset the CPU
begin
-- Generics allows polarity of switches/LEDs to be tweaked from the project file
sw_interrupt_n <= not sw1 when SW1ActiveHigh else sw1;
sw_reset_n <= not sw2 when SW2ActiveHigh else sw2;
led3 <= not led3_n when LEDsActiveHigh else led3_n;
led6 <= not led6_n when LEDsActiveHigh else led6_n;
led8 <= not led8_n when LEDsActiveHigh else led8_n;
inst_dcm0 : entity work.DCM0
generic map (
ClkMult => ClkMult,
@ -123,7 +107,7 @@ begin
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock49,
CLKIN_IN => clock,
CLKFX_OUT => clock_avr
);
@ -131,7 +115,8 @@ begin
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
avr_prog_mem_size => 1024 * 8
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
@ -153,11 +138,11 @@ begin
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw1 => not sw_interrupt_n,
nsw2 => sw_reset_n,
led3 => led3_n,
led6 => led6_n,
led8 => led8_n,
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
@ -211,9 +196,9 @@ begin
R_W_n <= R_W_n_int;
Addr <= Addr_int;
clk_gen : process(clock49)
clk_gen : process(clock)
begin
if rising_edge(clock49) then
if rising_edge(clock) then
Phi0_a <= Phi0;
Phi0_b <= Phi0_a;
Phi0_c <= Phi0_b;

181
src/MOS6502CpuMonALS.vhd Normal file
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@ -0,0 +1,181 @@
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonALS.vhd
-- /___/ /\ Timestamp : 20/09/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMonALS
--Device: XC6SLX9
--
--
-- This is a small wrapper around MOS6502CpuMon that add the following signals:
-- OEAH_n
-- OEAL_n
-- OED_n
-- DIRD
-- BE
-- ML_n
-- VP_n
-- (these are not fully implemented yet)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMonALS is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false;
num_comparators : integer := 8;
avr_prog_mem_size : integer := 8 * 1024
);
port (
clock : in std_logic;
-- 6502 Signals
PhiIn : in std_logic;
Phi1Out : out std_logic;
Phi2Out : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic_vector(1 downto 0);
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : inout std_logic;
Rdy : in std_logic;
-- 65C02 Signals
BE : in std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
-- Level Shifter Controls
OERW_n : out std_logic;
OEAH_n : out std_logic;
OEAL_n : out std_logic;
OED_n : out std_logic;
DIRD : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- ID/mode inputs
mode : in std_logic;
id : in std_logic_vector(3 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
-- OHO_DY1 LED display
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMonALS;
architecture behavioral of MOS6502CpuMonALS is
signal R_W_n_int : std_logic;
signal sw_interrupt : std_logic;
signal sw_reset : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_interrupt <= not sw1;
sw_reset <= not sw2;
led1 <= led_bkpt;
led2 <= led_trig0;
led3 <= led_trig1;
wrapper : entity work.MOS6502CpuMon
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock => clock,
-- 6502 Signals
Phi0 => PhiIn,
Phi1 => Phi1Out,
Phi2 => Phi2Out,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n_int,
Data => Data,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy,
-- External trigger inputs
trig => trig,
-- Jumpers
fakeTube_n => '1',
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 LED display
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
);
-- 6502 Outputs
R_W_n <= R_W_n_int & R_W_n_int;
-- 65C02 Outputs
ML_n <= '1';
VP_n <= '1';
-- Level Shifter Controls
OERW_n <= not (BE);
OEAH_n <= not (BE);
OEAL_n <= not (BE);
OED_n <= not (BE and PhiIn); -- TODO: might need to use a slightly delayed version of Phi2 here
DIRD <= R_W_n_int;
end behavioral;

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@ -1,5 +1,5 @@
------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
@ -7,34 +7,34 @@
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomBusMon.vhd
-- /___/ /\ Timestamp : 30/05/2015
-- / / Filename : MOS6502CpuMonCore.vhd
-- /___/ /\ Timestamp : 3/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomBusMon
--Device: XC3S250E
--Design Name: MOS6502CpuMonCore
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.OhoPack.all ;
entity MOS6502CpuMonCore is
generic (
UseT65Core : boolean;
UseAlanDCore : boolean;
avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
avr_prog_mem_size : integer := 1024 * 8 -- 6502 fits in 8K, others need 9K
-- default sizing is used by Electron/Beeb Fpga
num_comparators : integer := 8;
avr_prog_mem_size : integer := 1024 * 8
);
port (
clock_avr : in std_logic;
clock_avr : in std_logic;
busmon_clk : in std_logic;
busmon_clken : in std_logic;
cpu_clk : in std_logic;
cpu_clken : in std_logic;
busmon_clk : in std_logic;
busmon_clken : in std_logic;
cpu_clk : in std_logic;
cpu_clken : in std_logic;
-- 6502 Signals
IRQ_n : in std_logic;
@ -50,25 +50,25 @@ entity MOS6502CpuMonCore is
Rdy : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- GODIL Switches
sw1 : in std_logic;
nsw2 : in std_logic;
-- Switches
sw_interrupt : in std_logic;
sw_reset : in std_logic;
-- GODIL LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMonCore;
@ -113,11 +113,19 @@ architecture behavioral of MOS6502CpuMonCore is
signal NMI_n_masked : std_logic;
signal IRQ_n_masked : std_logic;
signal led_trig0_n : std_logic;
signal led_trig1_n : std_logic;
signal led_bkpt_n : std_logic;
begin
led_trig0 <= not led_trig0_n;
led_trig1 <= not led_trig1_n;
led_bkpt <= not led_bkpt_n;
mon : entity work.BusMonCore
generic map (
avr_data_mem_size => avr_data_mem_size,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
@ -140,11 +148,11 @@ begin
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw1 => sw1,
nsw2 => nsw2,
led3 => led3,
led6 => led6,
led8 => led8,
sw1 => sw_interrupt,
nsw2 => not sw_reset,
led3 => led_trig0_n,
led6 => led_trig1_n,
led8 => led_bkpt_n,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,

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src/MOS6502CpuMonGODIL.vhd Normal file
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@ -0,0 +1,144 @@
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonGODIL.vhd
-- /___/ /\ Timestamp : 03/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMonGODIL
--Device: XC3S250E and XC3S500E
--
-- Note: in 65C02 mode, BE, ML_n and VP_n are not implemented
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMonGODIL is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false;
num_comparators : integer := 8;
avr_prog_mem_size : integer := 8 * 1024
);
port (
clock49 : in std_logic;
-- 6502 Signals
Phi0 : in std_logic;
Phi1 : out std_logic;
Phi2 : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic;
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : inout std_logic;
Rdy : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Jumpers
fakeTube_n : in std_logic;
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 LED display
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMonGODIL;
architecture behavioral of MOS6502CpuMonGODIL is
signal sw_interrupt : std_logic;
signal sw_reset : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_interrupt <= sw1;
sw_reset <= not sw2;
led8 <= not led_bkpt;
led3 <= not led_trig0;
led6 <= not led_trig1;
wrapper : entity work.MOS6502CpuMon
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
ClkMult => 10,
ClkDiv => 31,
ClkPer => 20.345,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock => clock49,
-- 6502 Signals
Phi0 => Phi0,
Phi1 => Phi1,
Phi2 => Phi2,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n,
Data => Data,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy,
-- External trigger inputs
trig => trig,
-- Jumpers
fakeTube_n => fakeTube_n,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 LED display
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
);
end behavioral;

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src/MOS6502CpuMonLX9.vhd Normal file
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@ -0,0 +1,144 @@
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonLX9.vhd
-- /___/ /\ Timestamp : 03/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMonLX9
--Device: XC6SLX9
--
-- Note: in 65C02 mode, BE, ML_n and VP_n are not implemented
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMonLX9 is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false;
num_comparators : integer := 8;
avr_prog_mem_size : integer := 8 * 1024
);
port (
clock : in std_logic;
-- 6502 Signals
Phi0 : in std_logic;
Phi1 : out std_logic;
Phi2 : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic;
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : inout std_logic;
Rdy : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Jumpers
fakeTube_n : in std_logic;
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 LED display
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMonLX9;
architecture behavioral of MOS6502CpuMonLX9 is
signal sw_interrupt : std_logic;
signal sw_reset : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_interrupt <= sw1;
sw_reset <= sw2;
led8 <= led_bkpt;
led3 <= led_trig0;
led6 <= led_trig1;
wrapper : entity work.MOS6502CpuMon
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock => clock,
-- 6502 Signals
Phi0 => Phi0,
Phi1 => Phi1,
Phi2 => Phi2,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n,
Data => Data,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy,
-- External trigger inputs
trig => trig,
-- Jumpers
fakeTube_n => fakeTube_n,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_interrupt => sw_interrupt,
sw_reset => sw_reset,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 LED display
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
);
end behavioral;

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@ -1,174 +0,0 @@
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : W65C02CpuMon.vhd
-- /___/ /\ Timestamp : 20/09/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: W65C02CpuMon
--Device: XC6SLX9
--
--
-- This is a small wrapper around AtomCpuMon that add the following signals:
-- OEAH_n
-- OEAL_n
-- OED_n
-- DIRD
-- BE
-- ML_n
-- VP_n
-- (these are not fully implemented yet)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity W65C02CpuMon is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false;
LEDsActiveHigh : boolean := true; -- default value for EEPIZZA
SW1ActiveHigh : boolean := false; -- default value for EEPIZZA
SW2ActiveHigh : boolean := false; -- default value for EEPIZZA
ClkMult : integer := 8; -- default value for EEPIZZA
ClkDiv : integer := 25; -- default value for EEPIZZA
ClkPer : real := 16.000 -- default value for EEPIZZA
);
port (
clock : in std_logic;
-- 6502 Signals
PhiIn : in std_logic;
Phi1Out : out std_logic;
Phi2Out : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic_vector(1 downto 0);
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : inout std_logic;
Rdy : in std_logic;
-- 65C02 Signals
BE : in std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
-- Level Shifter Controls
OERW_n : out std_logic;
OEAH_n : out std_logic;
OEAL_n : out std_logic;
OED_n : out std_logic;
DIRD : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- ID/mode inputs
mode : in std_logic;
id : in std_logic_vector(3 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
-- OHO_DY1 LED display
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end W65C02CpuMon;
architecture behavioral of W65C02CpuMon is
signal R_W_n_int : std_logic;
begin
acm : entity work.AtomCpuMon
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
LEDsActiveHigh => LEDsActiveHigh,
SW1ActiveHigh => SW1ActiveHigh,
SW2ActiveHigh => SW2ActiveHigh,
ClkMult => ClkMult,
ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map (
clock49 => clock,
-- 6502 Signals
Phi0 => PhiIn,
Phi1 => Phi1Out,
Phi2 => Phi2Out,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n_int,
Data => Data,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy,
-- External trigger inputs
trig => trig,
-- Jumpers
fakeTube_n => '1',
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw1 => sw1,
sw2 => sw2,
-- LEDs
led3 => led2, -- trig 0
led6 => led3, -- trig 1
led8 => led1, -- break
-- OHO_DY1 LED display
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
);
-- 6502 Outputs
R_W_n <= R_W_n_int & R_W_n_int;
-- 65C02 Outputs
ML_n <= '1';
VP_n <= '1';
-- Level Shifter Controls
OERW_n <= not (BE);
OEAH_n <= not (BE);
OEAL_n <= not (BE);
OED_n <= not (BE and PhiIn); -- TODO: might need to use a slightly delayed version of Phi2 here
DIRD <= R_W_n_int;
end behavioral;

View File

@ -5,7 +5,7 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = AtomCpuMon
PROJECT = MOS6502CpuMonGODIL
# The target .bit file to be generated including the monitor program
TARGET = ice6502

View File

@ -2,50 +2,50 @@ NET "clock49" TNM_NET = clk_period_grp_49;
TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 500ns LOW;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
#NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 6
NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4
#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6
NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37
NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37
NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
@ -54,29 +54,18 @@ NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
# I/O's for test connector
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ;
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8

View File

@ -18,10 +18,6 @@
<file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../src/T6502/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
@ -257,6 +253,14 @@
<file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/MOS6502CpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../src/MOS6502CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
@ -366,9 +370,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomCpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MOS6502CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MOS6502CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MOS6502CpuMonGODIL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -426,7 +430,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -438,10 +442,10 @@
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@ -461,7 +465,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

View File

@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;

View File

@ -0,0 +1,15 @@
# The root directory of the project
ROOT = ../../..
# The common directory for makefile includes, etc.
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = MOS6502CpuMonGODIL
# The target .bit file to be generated including the monitor program
TARGET = ice65c02
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

View File

@ -0,0 +1,71 @@
NET "clock49" TNM_NET = clk_period_grp_49;
TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4
#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6
NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37
NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
# I/O's for test connector
#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ;

View File

@ -0,0 +1,585 @@
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<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-14T13:18:08" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="94463E018478C2B4E24AE2AD62D55F9D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

View File

@ -0,0 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

View File

@ -5,7 +5,7 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = AtomCpuMon
PROJECT = MOS6502CpuMonGODIL
# The target .bit file to be generated including the monitor program
TARGET = ice6502

View File

@ -2,50 +2,50 @@ NET "clock49" TNM_NET = clk_period_grp_49;
TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 500ns LOW;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
#NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 4
#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 | PULLUP ; # 6502 pin 6
NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4
#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6
NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37
NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37
NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
@ -54,29 +54,18 @@ NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
# I/O's for test connector
#NET tvs1 LOC=P48 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET tvs0 LOC=P49 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tmosi LOC=P27 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tdin LOC=P44 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
NET tcclk LOC=P50 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET tm1 LOC=P42 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET thsw LOC=P99 | IOSTANDARD = LVCMOS33 | DRIVE=16 ;
#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ;
# NET "" LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
# NET "" LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
# NET "" LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
# NET "" LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
# NET "" LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
# NET "" LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
# NET "" LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8

View File

@ -18,10 +18,6 @@
<file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../src/T6502/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
@ -257,6 +253,14 @@
<file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/MOS6502CpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../src/MOS6502CpuMonGODIL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
@ -286,7 +290,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@ -366,9 +370,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomCpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MOS6502CpuMonGODIL|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MOS6502CpuMonGODIL.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MOS6502CpuMonGODIL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -426,7 +430,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -438,10 +442,10 @@
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@ -461,7 +465,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

View File

@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;

View File

@ -0,0 +1,15 @@
# The root directory of the project
ROOT = ../../..
# The common directory for makefile includes, etc.
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = MOS6502CpuMonGODIL
# The target .bit file to be generated including the monitor program
TARGET = ice65c02
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

View File

@ -0,0 +1,71 @@
NET "clock49" TNM_NET = clk_period_grp_49;
TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.345ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "clock49" LOC="P89" | IOSTANDARD = LVCMOS33 ; # 49.152 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 ; # 6502 pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 ; # 6502 pin 2
NET "Phi1" LOC="P18" | IOSTANDARD = LVCMOS33 ; # 6502 pin 3
NET "IRQ_n" LOC="P17" | IOSTANDARD = LVCMOS33 ; # 6502 pin 4
#NET "NC" LOC="P94" | IOSTANDARD = LVCMOS33 ; # 6502 pin 5
NET "NMI_n" LOC="P22" | IOSTANDARD = LVCMOS33 ; # 6502 pin 6
NET "Sync" LOC="P23" | IOSTANDARD = LVCMOS33 ; # 6502 pin 7
#NET "VCC" LOC="P33" | IOSTANDARD = LVCMOS33 ; # 6502 pin 8
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 ; # 6502 pin 9
NET "Addr<1>" LOC="P34" | IOSTANDARD = LVCMOS33 ; # 6502 pin 10
NET "Addr<2>" LOC="P40" | IOSTANDARD = LVCMOS33 ; # 6502 pin 11
NET "Addr<3>" LOC="P41" | IOSTANDARD = LVCMOS33 ; # 6502 pin 12
NET "Addr<4>" LOC="P36" | IOSTANDARD = LVCMOS33 ; # 6502 pin 13
NET "Addr<5>" LOC="P35" | IOSTANDARD = LVCMOS33 ; # 6502 pin 14
NET "Addr<6>" LOC="P53" | IOSTANDARD = LVCMOS33 ; # 6502 pin 15
NET "Addr<7>" LOC="P54" | IOSTANDARD = LVCMOS33 ; # 6502 pin 16
NET "Addr<8>" LOC="P57" | IOSTANDARD = LVCMOS33 ; # 6502 pin 17
NET "Addr<9>" LOC="P58" | IOSTANDARD = LVCMOS33 ; # 6502 pin 18
NET "Addr<10>" LOC="P60" | IOSTANDARD = LVCMOS33 ; # 6502 pin 19
NET "Addr<11>" LOC="P61" | IOSTANDARD = LVCMOS33 ; # 6502 pin 20
#NET "VSS" LOC="P67" | IOSTANDARD = LVCMOS33 ; # 6502 pin 21
NET "Addr<12>" LOC="P68" | IOSTANDARD = LVCMOS33 ; # 6502 pin 22
NET "Addr<13>" LOC="P70" | IOSTANDARD = LVCMOS33 ; # 6502 pin 23
NET "Addr<14>" LOC="P71" | IOSTANDARD = LVCMOS33 ; # 6502 pin 24
NET "Addr<15>" LOC="P86" | IOSTANDARD = LVCMOS33 ; # 6502 pin 25
NET "Data<7>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # 6502 pin 26
NET "Data<6>" LOC="P83" | IOSTANDARD = LVCMOS33 ; # 6502 pin 27
NET "Data<5>" LOC="P78" | IOSTANDARD = LVCMOS33 ; # 6502 pin 28
NET "Data<4>" LOC="P79" | IOSTANDARD = LVCMOS33 ; # 6502 pin 29
NET "Data<3>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # 6502 pin 30
NET "Data<2>" LOC="P92" | IOSTANDARD = LVCMOS33 ; # 6502 pin 31
NET "Data<1>" LOC="P98" | IOSTANDARD = LVCMOS33 ; # 6502 pin 32
NET "Data<0>" LOC="P3" | IOSTANDARD = LVCMOS33 ; # 6502 pin 33
NET "R_W_n" LOC="P2" | IOSTANDARD = LVCMOS33 ; # 6502 pin 34
#NET "NC" LOC="P4" | IOSTANDARD = LVCMOS33 ; # 6502 pin 35
#NET "NC" LOC="P5" | IOSTANDARD = LVCMOS33 ; # 6502 pin 36
NET "Phi0" LOC="P90" | IOSTANDARD = LVCMOS33 ; # 6502 pin 37
NET "SO_n" LOC="P9" | IOSTANDARD = LVCMOS33 ; # 6502 pin 38
NET "Phi2" LOC="P10" | IOSTANDARD = LVCMOS33 ; # 6502 pin 39
NET "Res_n" LOC="P11" | IOSTANDARD = LVCMOS33 ; # 6502 pin 40
NET "led3" LOC="P43" | IOSTANDARD = LVCMOS33 ; # Red LED (near SW1)
NET "led6" LOC="P25" | IOSTANDARD = LVCMOS33 ; # Red LED (just left of FPGA)
NET "led8" LOC="P47" | IOSTANDARD = LVCMOS33 ; # Green LED (near SW1)
NET "sw1" LOC="P39" | IOSTANDARD = LVCMOS33 ; # Bottom Switch
NET "sw2" LOC="P69" | IOSTANDARD = LVCMOS33 | PULLUP ; # Top Switch
# I/O's for test connector
#NET tvs1 LOC="P48" | IOSTANDARD = LVCMOS33 ; # connector pin E2
#NET tvs0 LOC="P49" | IOSTANDARD = LVCMOS33 ; # connector pin E3
NET tmosi LOC="P27" | IOSTANDARD = LVCMOS33 ; # connector pin E4
NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 ; # connector pin E5
NET tcclk LOC="P50" | IOSTANDARD = LVCMOS33 ; # connector pin E6
#NET tm1 LOC="P42" | IOSTANDARD = LVCMOS33 ; # connector pin E7
#NET thsw LOC="P99" | IOSTANDARD = LVCMOS33 ; # connector pin E8
NET "avr_TxD" LOC="P26" | IOSTANDARD = LVCMOS33 ;
NET "avr_RxD" LOC="P15" | IOSTANDARD = LVCMOS33 ;
NET "trig<0>" LOC="P62" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P63" | IOSTANDARD = LVCMOS33 ;
NET "fakeTube_n" LOC="P65" | IOSTANDARD = LVCMOS33 ;

View File

@ -0,0 +1,585 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
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</file>
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</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
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</file>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
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<file xil_pn:name="../../../src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
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<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
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</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerDFF.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/resync/rsnc_comp_pack.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
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<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-14T13:18:08" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="94463E018478C2B4E24AE2AD62D55F9D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

View File

@ -0,0 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

View File

@ -5,7 +5,7 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = W65C02CpuMon
PROJECT = MOS6502CpuMonALS
# The target .bit file to be generated including the monitor program
TARGET = ice6502

View File

@ -18,7 +18,7 @@
<file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../src/MOS6502CpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
@ -257,7 +257,7 @@
<file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/W65C02CpuMon.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../src/MOS6502CpuMonALS.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
@ -384,9 +384,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|W65C02CpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/W65C02CpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/W65C02CpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MOS6502CpuMonALS|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MOS6502CpuMonALS.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MOS6502CpuMonALS" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -455,7 +455,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="W65C02CpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="MOS6502CpuMonALS" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -470,10 +470,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="W65C02CpuMon_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="W65C02CpuMon_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="W65C02CpuMon_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="W65C02CpuMon_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MOS6502CpuMonALS_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MOS6502CpuMonALS_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MOS6502CpuMonALS_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MOS6502CpuMonALS_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -497,7 +497,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="W65C02CpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MOS6502CpuMonALS" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

View File

@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;

View File

@ -5,7 +5,7 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = W65C02CpuMon
PROJECT = MOS6502CpuMonALS
# The target .bit file to be generated including the monitor program
TARGET = ice65c02

View File

@ -18,7 +18,7 @@
<file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../src/MOS6502CpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
@ -257,7 +257,7 @@
<file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/W65C02CpuMon.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../src/MOS6502CpuMonALS.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
@ -384,9 +384,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|W65C02CpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/W65C02CpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/W65C02CpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MOS6502CpuMonALS|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MOS6502CpuMonALS.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MOS6502CpuMonALS" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -455,7 +455,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="W65C02CpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="MOS6502CpuMonALS" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -470,10 +470,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="W65C02CpuMon_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="W65C02CpuMon_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="W65C02CpuMon_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="W65C02CpuMon_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="MOS6502CpuMonALS_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="MOS6502CpuMonALS_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="MOS6502CpuMonALS_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="MOS6502CpuMonALS_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -497,7 +497,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="W65C02CpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="MOS6502CpuMonALS" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

View File

@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
acm/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;

View File

@ -5,13 +5,13 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = AtomCpuMon
PROJECT = MOS6502CpuMonLX9
# The target .bit file to be generated including the monitor program
TARGET = ice6502
# Frequuency that the AVR runs at
F_CPU = 19354838
F_CPU = 16000000
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc

View File

@ -1,15 +1,15 @@
NET "clock49" TNM_NET = clk_period_grp_49;
TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.00ns HIGH;
NET "clock" TNM_NET = clk_period_grp_50;
TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 250ns LOW;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
#NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "Phi1" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
NET "IRQ_n" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
#NET "NC" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5

View File

@ -18,10 +18,6 @@
<file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../src/T6502/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
@ -257,6 +253,14 @@
<file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/MOS6502CpuMonLX9.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../../src/MOS6502CpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
@ -370,7 +374,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
@ -380,9 +384,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomCpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MOS6502CpuMonLX9|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MOS6502CpuMonLX9.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MOS6502CpuMonLX9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -451,7 +455,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -466,10 +470,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -493,7 +497,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

View File

@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;

View File

@ -0,0 +1,18 @@
# The root directory of the project
ROOT = ../../..
# The common directory for makefile includes, etc.
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = MOS6502CpuMonLX9
# The target .bit file to be generated including the monitor program
TARGET = ice65c02
# Frequuency that the AVR runs at
F_CPU = 16000000
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

View File

@ -0,0 +1,74 @@
NET "clock" TNM_NET = clk_period_grp_50;
TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
NET "Rdy" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "Phi1" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
NET "IRQ_n" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
#NET "NC" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
NET "NMI_n" LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
NET "Sync" LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
#NET "VCC" LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
NET "Addr<0>" LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
NET "Addr<1>" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
NET "Addr<2>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
NET "Addr<3>" LOC="P88" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
NET "Addr<4>" LOC="P87" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
NET "Addr<5>" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
NET "Addr<6>" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
NET "Addr<7>" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
NET "Addr<8>" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
NET "Addr<9>" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
NET "Addr<10>" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
NET "Addr<11>" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
NET "Addr<12>" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
NET "Addr<13>" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
NET "Addr<14>" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
NET "Addr<15>" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
NET "Data<7>" LOC="P26" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
NET "Data<6>" LOC="P29" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
NET "Data<5>" LOC="P24" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
NET "Data<4>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
NET "Data<3>" LOC="P21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
NET "Data<2>" LOC="P1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
NET "Data<1>" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
NET "Data<0>" LOC="P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
NET "R_W_n" LOC="P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
#NET "NC" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
#NET "NC" LOC="P6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
NET "Phi0" LOC="P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
NET "SO_n" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
NET "Phi2" LOC="P14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
NET "Res_n" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
# LEDs and Switches
NET "led3" LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
NET "led6" LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
NET "led8" LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
NET "sw1" LOC="P132" | IOSTANDARD = LVCMOS33 ; # reset
NET "sw2" LOC="P131" | IOSTANDARD = LVCMOS33 ; # interrupt
# 7-segment LED
NET tmosi LOC="P45" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# UART
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs
NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P127" | IOSTANDARD = LVCMOS33 ;
# Jumpers
NET "fakeTube_n" LOC="P112" | IOSTANDARD = LVCMOS33 | PULLUP ;

View File

@ -0,0 +1,626 @@
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<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-14T13:18:08" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="94463E018478C2B4E24AE2AD62D55F9D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

View File

@ -0,0 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

View File

@ -5,13 +5,13 @@ ROOT = ../../..
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = AtomCpuMon
PROJECT = MOS6502CpuMonLX9
# The target .bit file to be generated including the monitor program
TARGET = ice6502
# Frequuency that the AVR runs at
F_CPU = 19354838
F_CPU = 16000000
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc

View File

@ -1,15 +1,15 @@
NET "clock49" TNM_NET = clk_period_grp_49;
TIMESPEC TS_clk_period_49 = PERIOD "clk_period_grp_49" 20.00ns HIGH;
NET "clock" TNM_NET = clk_period_grp_50;
TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 250ns LOW;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock49" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
#NET "Rdy" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "Rdy" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "Phi1" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
NET "IRQ_n" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
#NET "NC" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5

View File

@ -18,10 +18,6 @@
<file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../src/T6502/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
@ -257,6 +253,14 @@
<file xil_pn:name="memory.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/MOS6502CpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../src/MOS6502CpuMonLX9.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../ipcore/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
@ -370,7 +374,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
@ -380,9 +384,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AtomCpuMon|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/AtomCpuMon.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|MOS6502CpuMonLX9|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../src/MOS6502CpuMonLX9.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/MOS6502CpuMonLX9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -451,7 +455,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -466,10 +470,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -493,7 +497,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>

View File

@ -2,35 +2,35 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;

View File

@ -0,0 +1,18 @@
# The root directory of the project
ROOT = ../../..
# The common directory for makefile includes, etc.
COMMON = ../../common
# The project .bit file produced by the Xilinx .xise project
PROJECT = MOS6502CpuMonLX9
# The target .bit file to be generated including the monitor program
TARGET = ice65c02
# Frequuency that the AVR runs at
F_CPU = 16000000
# Common include files
include $(COMMON)/Makefile_$(TARGET).inc
include $(COMMON)/Makefile.inc

View File

@ -0,0 +1,74 @@
NET "clock" TNM_NET = clk_period_grp_50;
TIMESPEC TS_clk_period_50 = PERIOD "clk_period_grp_50" 20.00ns HIGH;
NET "Phi0" TNM_NET = clk_period_grp_phi0;
TIMESPEC TS_clk_period_phi0 = PERIOD "clk_period_grp_phi0" 125ns LOW;
NET "Phi0" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clock" LOC="P50" | IOSTANDARD = LVCMOS33 | PERIOD = 20.00ns ; # 50.00 MHz Oscillator
#NET "VSS" LOC="P16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 1
NET "Rdy" LOC="P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 2
NET "Phi1" LOC="P17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 3
NET "IRQ_n" LOC="P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 4
#NET "NC" LOC="P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 5
NET "NMI_n" LOC="P26" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 6
NET "Sync" LOC="P29" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 7
#NET "VCC" LOC="P24" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 8
NET "Addr<0>" LOC="P32" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 9
NET "Addr<1>" LOC="P21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 10
NET "Addr<2>" LOC="P1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 11
NET "Addr<3>" LOC="P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 12
NET "Addr<4>" LOC="P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 13
NET "Addr<5>" LOC="P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 14
NET "Addr<6>" LOC="P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 15
NET "Addr<7>" LOC="P6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 16
NET "Addr<8>" LOC="P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 17
NET "Addr<9>" LOC="P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 18
NET "Addr<10>" LOC="P14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 19
NET "Addr<11>" LOC="P12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 20
#NET "VSS" LOC="P94" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 21
NET "Addr<12>" LOC="P95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 22
NET "Addr<13>" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 23
NET "Addr<14>" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 24
NET "Addr<15>" LOC="P100" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 25
NET "Data<7>" LOC="P101" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 26
NET "Data<6>" LOC="P104" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 27
NET "Data<5>" LOC="P102" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 28
NET "Data<4>" LOC="P111" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 29
NET "Data<3>" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 30
NET "Data<2>" LOC="P78" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 31
NET "Data<1>" LOC="P88" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 32
NET "Data<0>" LOC="P87" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 33
NET "R_W_n" LOC="P85" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 34
#NET "NC" LOC="P84" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 35
#NET "NC" LOC="P83" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 36
NET "Phi0" LOC="P82" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 37
NET "SO_n" LOC="P80" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 38
NET "Phi2" LOC="P92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 39
NET "Res_n" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # dip pin 40
# LEDs and Switches
NET "led3" LOC="P134" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
NET "led6" LOC="P119" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
NET "led8" LOC="P117" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
NET "sw1" LOC="P132" | IOSTANDARD = LVCMOS33 ; # reset
NET "sw2" LOC="P131" | IOSTANDARD = LVCMOS33 ; # interrupt
# 7-segment LED
NET tmosi LOC="P45" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tdin LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET tcclk LOC="P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# UART
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs
NET "trig<0>" LOC="P126" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P127" | IOSTANDARD = LVCMOS33 ;
# Jumpers
NET "fakeTube_n" LOC="P112" | IOSTANDARD = LVCMOS33 | PULLUP ;

View File

@ -0,0 +1,626 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="board.ucf" xil_pn:type="FILE_UCF">
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</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../../src/T6502/T65_MCode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../../src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
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<file xil_pn:name="../../../src/AVR8/Core/io_adr_dec.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../src/AVR8/Core/io_reg_file.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../src/AVR8/Core/pm_fetch_dec.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGProgrammerPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/JTAGTAPCtrlSMPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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<file xil_pn:name="../../../src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/Peripheral/SynchronizerDFF.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../../src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
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<file xil_pn:name="../../../src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../../src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
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<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AtomCpuMon_map.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AtomCpuMon_timesim.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AtomCpuMon_synthesis.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AtomCpuMon_translate.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="working" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AtomCpuMon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-06-14T13:18:08" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="94463E018478C2B4E24AE2AD62D55F9D" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

View File

@ -0,0 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
wrapper/core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;