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Updated XDM2Kx8 to a more portable implementation
Change-Id: I37cbe56b7b0113e24855eb1c0fcf7bbe006eefd3
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@@ -1,25 +1,9 @@
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--************************************************************************************************
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-- 2Kx8(16 KB) DM RAM for AVR Core(Xilinx)
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-- Version 0.2
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-- Designed by Ruslan Lepetenok
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-- Jack Gassett for use with Papilio
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-- Modified 30.07.2005
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--************************************************************************************************
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use WORK.SynthCtrlPack.all; -- Synthesis control
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use WORK.SynthCtrlPack.all; -- Synthesis control
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-- For Synplicity Synplify
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--library virtexe;
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--use virtexe.components.all;
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-- Aldec
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library unisim;
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use unisim.vcomponents.all;
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entity XDM2Kx8 is port(
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entity XDM2Kx8 is port(
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cp2 : in std_logic;
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cp2 : in std_logic;
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ce : in std_logic;
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ce : in std_logic;
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@@ -32,35 +16,22 @@ end XDM2Kx8;
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architecture RTL of XDM2Kx8 is
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architecture RTL of XDM2Kx8 is
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signal RAMBlDOut : std_logic_vector(dout'range);
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type ram_type is array (2**(CDATAMEMSIZE+1)-1 downto 0) of std_logic_vector (7 downto 0);
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signal WEB : std_logic;
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signal RAM : ram_type;
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signal cp2n : std_logic;
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signal gnd : std_logic;
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signal DIP : STD_LOGIC_VECTOR(0 downto 0) := "1";
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signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
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begin
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begin
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gnd <= '0';
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process (cp2)
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begin
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WEB <= '1' when we='1' else '0';
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if rising_edge(cp2) then
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if ce = '1' then
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if (we = '1') then
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RAM_Byte:component RAMB16_S9 port map(
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RAM(conv_integer(address)) <= din;
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DO => RAMBlDOut(7 downto 0),
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end if;
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ADDR => address(10 downto 0),
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dout <= RAM(conv_integer(address));
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DI => din(7 downto 0),
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end if;
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DIP => DIP,
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end if;
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EN => ce,
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end process;
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SSR => SSR,
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CLK => cp2,
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WE => WEB
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);
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-- Output data mux
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dout <= RAMBlDOut;
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end RTL;
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end RTL;
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