6502/AtomBusMon
1
0
Fork 0
mirror of https://github.com/hoglet67/AtomBusMon.git synced 2025-01-04 22:29:30 +00:00
Code Issues Projects Releases Wiki Activity

6502: minor fixes to lx9_dave, boots in beeb

Browse Source 
Change-Id: I18c909f7586b439d52ecc938d4a9bb7a3e6d76e5
This commit is contained in:
David Banks 2019-10-03 12:38:50 +01:00
parent c08084d703
commit dfeaff9488
4 changed files with 20 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/lx9_dave/ice6502/Makefile
View File

@ -11,7 +11,7 @@ PROJECT = W65C02CpuMon
TARGET = ice6502 TARGET = ice6502
# Frequuency that the AVR runs at # Frequuency that the AVR runs at
F_CPU = 19354838 F_CPU = 16000000
# Common include files # Common include files
include $(COMMON)/Makefile_$(TARGET).inc include $(COMMON)/Makefile_$(TARGET).inc

24
target/lx9_dave/ice6502/board.ucf
View File

@ -62,23 +62,23 @@ NET "DIRD" LOC="P93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "led1" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint NET "led1" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
NET "led2" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active NET "led2" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
NET "led3" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active NET "led3" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
NET "sw1" LOC="P45" | IOSTANDARD = LVCMOS33 ; # reset NET "sw1" LOC="P45" | IOSTANDARD = LVCMOS33 | PULLUP ; # reset
NET "sw2" LOC="P66" | IOSTANDARD = LVCMOS33 ; # interrupt NET "sw2" LOC="P66" | IOSTANDARD = LVCMOS33 | PULLUP ; # interrupt
# ID/Jumper # ID/Jumper
NET "mode" LOC="P140" | IOSTANDARD = LVCMOS33 ; # mode jumper NET "mode" LOC="P140" | IOSTANDARD = LVCMOS33 | PULLUP ; # mode jumper
NET "id<0>" LOC="P88 " | IOSTANDARD = LVCMOS33 ; # id links NET "id<0>" LOC="P88 " | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
NET "id<1>" LOC="P87 " | IOSTANDARD = LVCMOS33 ; # id links NET "id<1>" LOC="P87 " | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
NET "id<2>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # id links NET "id<2>" LOC="P85" | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
NET "id<3>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # id links NET "id<3>" LOC="P84" | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
# UART # UART
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ; NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs # External trigger inputs
NET "trig<0>" LOC="P127" | IOSTANDARD = LVCMOS33 ; NET "trig<0>" LOC="P116" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P126" | IOSTANDARD = LVCMOS33 ; NET "trig<1>" LOC="P123" | IOSTANDARD = LVCMOS33 ;
# 7-segment LED (connect to J5 on FPGA board) # 7-segment LED (connect to J5 on FPGA board)
NET "tmosi" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "tmosi" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
@ -90,9 +90,3 @@ NET "tcclk" LOC="P62" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; #NET "test2" LOC="P48" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; #NET "test3" LOC="P57" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; #NET "test4" LOC="P59" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

2
target/lx9_dave/ice6502/ice6502.xise
View File

@ -374,7 +374,7 @@
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="SW2ActiveHigh=true LEDsActiveHigh=true ClkMult=12 ClkDiv=31 ClkPer=20.0" xil_pn:valueState="non-default"/> <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>

18
target/lx9_dave/icez80/board.ucf
View File

@ -59,23 +59,23 @@ NET "DIRD" LOC="P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "led1" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint NET "led1" LOC="P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # stopped at breakpoint
NET "led2" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active NET "led2" LOC="P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 0 active
NET "led3" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active NET "led3" LOC="P67" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; # trigger 1 active
NET "sw1" LOC="P45" | IOSTANDARD = LVCMOS33 ; # reset NET "sw1" LOC="P45" | IOSTANDARD = LVCMOS33 | PULLUP ; # reset
NET "sw2" LOC="P66" | IOSTANDARD = LVCMOS33 ; # interrupt NET "sw2" LOC="P66" | IOSTANDARD = LVCMOS33 | PULLUP ; # interrupt
# ID/Jumper # ID/Jumper
NET "mode" LOC="P140" | IOSTANDARD = LVCMOS33 ; # mode jumper NET "mode" LOC="P140" | IOSTANDARD = LVCMOS33 | PULLUP ; # mode jumper
NET "id<0>" LOC="P88 " | IOSTANDARD = LVCMOS33 ; # id links NET "id<0>" LOC="P88 " | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
NET "id<1>" LOC="P87 " | IOSTANDARD = LVCMOS33 ; # id links NET "id<1>" LOC="P87 " | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
NET "id<2>" LOC="P85" | IOSTANDARD = LVCMOS33 ; # id links NET "id<2>" LOC="P85" | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
NET "id<3>" LOC="P84" | IOSTANDARD = LVCMOS33 ; # id links NET "id<3>" LOC="P84" | IOSTANDARD = LVCMOS33 | PULLUP ; # id links
# UART # UART
NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "avr_TxD" LOC="P51" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ; NET "avr_RxD" LOC="P55" | IOSTANDARD = LVCMOS33 ;
# External trigger inputs # External trigger inputs
NET "trig<0>" LOC="P127" | IOSTANDARD = LVCMOS33 ; NET "trig<0>" LOC="P116" | IOSTANDARD = LVCMOS33 ;
NET "trig<1>" LOC="P126" | IOSTANDARD = LVCMOS33 ; NET "trig<1>" LOC="P123" | IOSTANDARD = LVCMOS33 ;
# 7-segment LED (connect to J5 on FPGA board) # 7-segment LED (connect to J5 on FPGA board)
NET "tmosi" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "tmosi" LOC="P58" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;