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Code Issues Projects Releases Wiki Activity

Made AVR XPM and XDM more generic

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Change-Id: I0025d56d4ba7fa3e20d73f09ac51068ffd1859c5
This commit is contained in:
David Banks 2015-11-28 17:22:23 +00:00
parent cc6c062b4b
commit e63266f720
35 changed files with 8789 additions and 3956 deletions
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1
.gitignore vendored
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@ -1,3 +1,4 @@
not_in_git/
iseconfig/
working/
nohup.out

103
AtomBusMon.xise
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@ -17,47 +17,47 @@
<files>
<file xil_pn:name="src/AtomBusMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="src/AVR8/Core/avr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="src/AVR8/Core/alu_avr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="src/AVR8/Core/bit_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="src/AVR8/Core/io_adr_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="src/AVR8/Core/io_reg_file.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="src/AVR8/Core/pm_fetch_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
@ -65,7 +65,7 @@
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
@ -81,51 +81,43 @@
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="src/AVR8/Memory/prog_mem_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XMemCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
@ -141,11 +133,11 @@
</file>
<file xil_pn:name="src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
@ -157,39 +149,39 @@
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/AVRuCPackage.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
@ -197,7 +189,7 @@
</file>
<file xil_pn:name="src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/SynthCtrlPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
@ -205,41 +197,41 @@
</file>
<file xil_pn:name="src/AVR8/Core/AVR_Core_CompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="src/AtomBusMon.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="src/AtomBusMon.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XDM2Kx8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XPM9Kx16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XPM_Xilinx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@ -424,6 +416,7 @@
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>

120
AtomCpuMon.xise
View File

@ -20,35 +20,35 @@
</file>
<file xil_pn:name="src/AtomCpuMon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="src/T6502/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="src/T6502/T65_MCode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="src/T6502/T65_Pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="src/T6502/T65.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/AVRuCPackage.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
@ -56,11 +56,11 @@
</file>
<file xil_pn:name="src/AVR8/CommonPacks/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="src/AVR8/CommonPacks/SynthCtrlPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
@ -68,39 +68,39 @@
</file>
<file xil_pn:name="src/AVR8/Core/alu_avr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
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<file xil_pn:name="src/AVR8/Core/AVR_Core_CompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
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<file xil_pn:name="src/AVR8/Core/avr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="src/AVR8/Core/bit_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="src/AVR8/Core/io_adr_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="src/AVR8/Core/io_reg_file.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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</file>
<file xil_pn:name="src/AVR8/Core/pm_fetch_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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</file>
<file xil_pn:name="src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
@ -108,7 +108,7 @@
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
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</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
@ -124,51 +124,43 @@
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
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</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
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</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
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<file xil_pn:name="src/AVR8/Memory/prog_mem_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XMemCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
@ -184,11 +176,11 @@
</file>
<file xil_pn:name="src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
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<file xil_pn:name="src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
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<file xil_pn:name="src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
@ -200,70 +192,70 @@
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/MOS6502CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/Memory/XPM_Xilinx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
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<file xil_pn:name="src/AtomCpuMon.bmm" xil_pn:type="FILE_BMM">
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</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>

116
AtomFast6502.xise
View File

@ -20,35 +20,35 @@
</file>
<file xil_pn:name="src/AtomFast6502.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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</file>
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</file>
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<file xil_pn:name="src/oho_dy1/Oho_Dy1.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/oho_dy1/OhoPack.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="src/AVR8/CommonPacks/avr_adr_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
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</file>
<file xil_pn:name="src/AVR8/CommonPacks/AVRuCPackage.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
@ -56,11 +56,11 @@
</file>
<file xil_pn:name="src/AVR8/CommonPacks/spi_mod_comp_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
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<file xil_pn:name="src/AVR8/CommonPacks/std_library.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="src/AVR8/CommonPacks/SynthCtrlPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
@ -68,39 +68,39 @@
</file>
<file xil_pn:name="src/AVR8/Core/alu_avr.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/Core/io_reg_file.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/Core/pm_fetch_dec.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/Core/reg_file.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
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<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
@ -108,7 +108,7 @@
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGOCDPrgTop.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/JTAGPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
@ -124,51 +124,43 @@
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgcp2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/OCDProgTCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_cp2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/ArbiterAndMux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemAccessCtrlPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/MemRdMux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="src/AVR8/MemArbAndMux/RAMAdrDcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="src/AVR8/Memory/prog_mem_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XMemCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/portx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/SynchronizerCompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
@ -184,11 +176,11 @@
</file>
<file xil_pn:name="src/AVR8/Peripheral/Timer_Counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="src/AVR8/Peripheral/uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="src/AVR8/resync/rsnc_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
@ -200,74 +192,74 @@
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_mod.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="src/AVR8/spi_mod/spi_slv_sel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="src/AVR8/uC/AVR_uC_CompPack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="src/AVR8/uC/AVR8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="src/AVR8/uC/external_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="src/AVR8/uC/ExtIRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="src/AVR8/uC/RAMDataReg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="src/AVR8/uC/ResetGenerator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="src/DCM/DCM0.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="src/AtomFast6502.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/BusMonCore.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="src/AlanD/R65Cx2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XDM2Kx8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XPM9Kx16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="src/MOS6502CpuMonCore.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="src/DCM/DCM2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XPM_Xilinx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>

8
MC6809ECpuMon.xise
View File

@ -229,12 +229,12 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XDM2Kx8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
<file xil_pn:name="src/AVR8/Memory/XDM_Generic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="src/AVR8/Memory/XPM9Kx16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
<file xil_pn:name="src/AVR8/Memory/XPM_Xilinx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="ipcore_dir/WatchEvents.xise" xil_pn:type="FILE_COREGENISE">

85
src/AVR8/CommonPacks/SynthCtrlPack.vhd
View File

@ -1,34 +1,51 @@
-- *****************************************************************************************
-- AVR synthesis control package
-- Version 1.32 (Special version for the JTAG OCD)
-- Modified 14.07.2005
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package SynthCtrlPack is
-- Please note: Do not change these settings, this is not quite ready yet. Jack Gassett
-- Control the size of Program and Data memory.
constant CDATAMEMSIZE : integer := 10; --2^(x+1)=Data SRAM Memory Size (10=2048) (Default 11=4096) (12=8192)
constant CPROGMEMSIZE : integer := 13; --(2^(x+1))*2)=Program Memory Size (10=4096) (11=8192) (Default 12=16384)
-- Calculate at Wolfram Alpha (http://www.wolframalpha.com/input/?i=%282^%28x%2B1%29%29*2%29%2Cx%3D12)
-- Reset generator
constant CSecondClockUsed : boolean := FALSE;
constant CImplClockSw : boolean := FALSE;
-- Only for ASICs
constant CSynchLatchUsed : boolean := FALSE;
-- Register file
constant CResetRegFile : boolean := TRUE;
-- External multiplexer size
constant CExtMuxInSize : positive := 16;
end SynthCtrlPack;
-- *****************************************************************************************
-- AVR synthesis control package
-- Version 1.32 (Special version for the JTAG OCD)
-- Modified 14.07.2005
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package SynthCtrlPack is
-- Function f_log2 returns the number of bits required to express
-- an unsigned integer in binary. It is used, for example, to
-- returns the width of a memory address bus, given the memory
-- depth in words
-- Function definition
function f_log2 (x : positive) return natural;
-- Reset generator
constant CSecondClockUsed : boolean := FALSE;
constant CImplClockSw : boolean := FALSE;
-- Only for ASICs
constant CSynchLatchUsed : boolean := FALSE;
-- Register file
constant CResetRegFile : boolean := TRUE;
-- External multiplexer size
constant CExtMuxInSize : positive := 16;
end SynthCtrlPack;
package body SynthCtrlPack is
-- Function body
function f_log2 (x : positive) return natural is
variable i : natural;
begin
i := 0;
while (2**i < x) and i < 31 loop
i := i + 1;
end loop;
return i;
end function;
end SynthCtrlPack;

65
src/AVR8/Memory/XDM16Kx8.vhd
View File

@ -1,65 +0,0 @@
--************************************************************************************************
-- 16Kx8(16 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM16Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM16Kx8;
architecture RTL of XDM16Kx8 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-9)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_Byte:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEB(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;

37
src/AVR8/Memory/XDM2Kx8.vhd
View File

@ -1,37 +0,0 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
entity XDM2Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CDATAMEMSIZE downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM2Kx8;
architecture RTL of XDM2Kx8 is
type ram_type is array (2**(CDATAMEMSIZE+1)-1 downto 0) of std_logic_vector (7 downto 0);
signal RAM : ram_type;
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;

65
src/AVR8/Memory/XDM32Kx8.vhd
View File

@ -1,65 +0,0 @@
--************************************************************************************************
-- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM32Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(14 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM32Kx8;
architecture RTL of XDM32Kx8 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-9)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_Byte:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEB(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;

73
src/AVR8/Memory/XDM4Kx8.vhd
View File

@ -1,73 +0,0 @@
--************************************************************************************************
-- 4Kx8(16 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Jack Gassett for use with Papilio
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM4Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CDATAMEMSIZE downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM4Kx8;
architecture RTL of XDM4Kx8 is
type RAMBlDOut_Type is array(2**(address'length-11)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-11)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 11)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-11)-1 generate
RAM_Byte:component RAMB16_S9 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(10 downto 0),
DI => din(7 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 11)));
end RTL;

43
src/AVR8/Memory/XDM_Generic.vhd Normal file
View File

@ -0,0 +1,43 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XDM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XDM is
type ram_type is array (0 to SIZE - 1) of std_logic_vector (WIDTH - 1 downto 0);
signal RAM : ram_type;
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;

60
src/AVR8/Memory/XMemCompPack.vhd
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@ -1,60 +0,0 @@
--************************************************************************************************
-- PM/DM memory components declarations for AVR core (Xilinx)
-- Version 0.4
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package XMemCompPack is
component XPM16Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
weh : in std_logic;
wel : in std_logic
);
end component;
component XDM16Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end component;
component XDM32Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(14 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end component;
-- XPM8Kx16 was moved to the top level
component XPM4Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(11 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end component;
-- XDM4Kx8 was moved to the top level
end XMemCompPack;

912
src/AVR8/Memory/XPM10Kx16.vhd
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@ -1,912 +0,0 @@
--************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM10Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM10Kx16;
architecture RTL of XPM10Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word0:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word0_INIT_00,
INIT_01 => PM_Inst_RAM_Word0_INIT_01,
INIT_02 => PM_Inst_RAM_Word0_INIT_02,
INIT_03 => PM_Inst_RAM_Word0_INIT_03,
INIT_04 => PM_Inst_RAM_Word0_INIT_04,
INIT_05 => PM_Inst_RAM_Word0_INIT_05,
INIT_06 => PM_Inst_RAM_Word0_INIT_06,
INIT_07 => PM_Inst_RAM_Word0_INIT_07,
INIT_08 => PM_Inst_RAM_Word0_INIT_08,
INIT_09 => PM_Inst_RAM_Word0_INIT_09,
INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
INIT_10 => PM_Inst_RAM_Word0_INIT_10,
INIT_11 => PM_Inst_RAM_Word0_INIT_11,
INIT_12 => PM_Inst_RAM_Word0_INIT_12,
INIT_13 => PM_Inst_RAM_Word0_INIT_13,
INIT_14 => PM_Inst_RAM_Word0_INIT_14,
INIT_15 => PM_Inst_RAM_Word0_INIT_15,
INIT_16 => PM_Inst_RAM_Word0_INIT_16,
INIT_17 => PM_Inst_RAM_Word0_INIT_17,
INIT_18 => PM_Inst_RAM_Word0_INIT_18,
INIT_19 => PM_Inst_RAM_Word0_INIT_19,
INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
INIT_20 => PM_Inst_RAM_Word0_INIT_20,
INIT_21 => PM_Inst_RAM_Word0_INIT_21,
INIT_22 => PM_Inst_RAM_Word0_INIT_22,
INIT_23 => PM_Inst_RAM_Word0_INIT_23,
INIT_24 => PM_Inst_RAM_Word0_INIT_24,
INIT_25 => PM_Inst_RAM_Word0_INIT_25,
INIT_26 => PM_Inst_RAM_Word0_INIT_26,
INIT_27 => PM_Inst_RAM_Word0_INIT_27,
INIT_28 => PM_Inst_RAM_Word0_INIT_28,
INIT_29 => PM_Inst_RAM_Word0_INIT_29,
INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word0_INIT_30,
INIT_31 => PM_Inst_RAM_Word0_INIT_31,
INIT_32 => PM_Inst_RAM_Word0_INIT_32,
INIT_33 => PM_Inst_RAM_Word0_INIT_33,
INIT_34 => PM_Inst_RAM_Word0_INIT_34,
INIT_35 => PM_Inst_RAM_Word0_INIT_35,
INIT_36 => PM_Inst_RAM_Word0_INIT_36,
INIT_37 => PM_Inst_RAM_Word0_INIT_37,
INIT_38 => PM_Inst_RAM_Word0_INIT_38,
INIT_39 => PM_Inst_RAM_Word0_INIT_39,
INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
INIT_3F => PM_Inst_RAM_Word0_INIT_3F
)
port map(
DO => RAMBlDOut(0)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(0)
);
RAM_Word1:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word1_INIT_00,
INIT_01 => PM_Inst_RAM_Word1_INIT_01,
INIT_02 => PM_Inst_RAM_Word1_INIT_02,
INIT_03 => PM_Inst_RAM_Word1_INIT_03,
INIT_04 => PM_Inst_RAM_Word1_INIT_04,
INIT_05 => PM_Inst_RAM_Word1_INIT_05,
INIT_06 => PM_Inst_RAM_Word1_INIT_06,
INIT_07 => PM_Inst_RAM_Word1_INIT_07,
INIT_08 => PM_Inst_RAM_Word1_INIT_08,
INIT_09 => PM_Inst_RAM_Word1_INIT_09,
INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
INIT_10 => PM_Inst_RAM_Word1_INIT_10,
INIT_11 => PM_Inst_RAM_Word1_INIT_11,
INIT_12 => PM_Inst_RAM_Word1_INIT_12,
INIT_13 => PM_Inst_RAM_Word1_INIT_13,
INIT_14 => PM_Inst_RAM_Word1_INIT_14,
INIT_15 => PM_Inst_RAM_Word1_INIT_15,
INIT_16 => PM_Inst_RAM_Word1_INIT_16,
INIT_17 => PM_Inst_RAM_Word1_INIT_17,
INIT_18 => PM_Inst_RAM_Word1_INIT_18,
INIT_19 => PM_Inst_RAM_Word1_INIT_19,
INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
INIT_20 => PM_Inst_RAM_Word1_INIT_20,
INIT_21 => PM_Inst_RAM_Word1_INIT_21,
INIT_22 => PM_Inst_RAM_Word1_INIT_22,
INIT_23 => PM_Inst_RAM_Word1_INIT_23,
INIT_24 => PM_Inst_RAM_Word1_INIT_24,
INIT_25 => PM_Inst_RAM_Word1_INIT_25,
INIT_26 => PM_Inst_RAM_Word1_INIT_26,
INIT_27 => PM_Inst_RAM_Word1_INIT_27,
INIT_28 => PM_Inst_RAM_Word1_INIT_28,
INIT_29 => PM_Inst_RAM_Word1_INIT_29,
INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word1_INIT_30,
INIT_31 => PM_Inst_RAM_Word1_INIT_31,
INIT_32 => PM_Inst_RAM_Word1_INIT_32,
INIT_33 => PM_Inst_RAM_Word1_INIT_33,
INIT_34 => PM_Inst_RAM_Word1_INIT_34,
INIT_35 => PM_Inst_RAM_Word1_INIT_35,
INIT_36 => PM_Inst_RAM_Word1_INIT_36,
INIT_37 => PM_Inst_RAM_Word1_INIT_37,
INIT_38 => PM_Inst_RAM_Word1_INIT_38,
INIT_39 => PM_Inst_RAM_Word1_INIT_39,
INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
INIT_3F => PM_Inst_RAM_Word1_INIT_3F
)
port map(
DO => RAMBlDOut(1)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(1)
);
RAM_Word2:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word2_INIT_00,
INIT_01 => PM_Inst_RAM_Word2_INIT_01,
INIT_02 => PM_Inst_RAM_Word2_INIT_02,
INIT_03 => PM_Inst_RAM_Word2_INIT_03,
INIT_04 => PM_Inst_RAM_Word2_INIT_04,
INIT_05 => PM_Inst_RAM_Word2_INIT_05,
INIT_06 => PM_Inst_RAM_Word2_INIT_06,
INIT_07 => PM_Inst_RAM_Word2_INIT_07,
INIT_08 => PM_Inst_RAM_Word2_INIT_08,
INIT_09 => PM_Inst_RAM_Word2_INIT_09,
INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
INIT_10 => PM_Inst_RAM_Word2_INIT_10,
INIT_11 => PM_Inst_RAM_Word2_INIT_11,
INIT_12 => PM_Inst_RAM_Word2_INIT_12,
INIT_13 => PM_Inst_RAM_Word2_INIT_13,
INIT_14 => PM_Inst_RAM_Word2_INIT_14,
INIT_15 => PM_Inst_RAM_Word2_INIT_15,
INIT_16 => PM_Inst_RAM_Word2_INIT_16,
INIT_17 => PM_Inst_RAM_Word2_INIT_17,
INIT_18 => PM_Inst_RAM_Word2_INIT_18,
INIT_19 => PM_Inst_RAM_Word2_INIT_19,
INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
INIT_20 => PM_Inst_RAM_Word2_INIT_20,
INIT_21 => PM_Inst_RAM_Word2_INIT_21,
INIT_22 => PM_Inst_RAM_Word2_INIT_22,
INIT_23 => PM_Inst_RAM_Word2_INIT_23,
INIT_24 => PM_Inst_RAM_Word2_INIT_24,
INIT_25 => PM_Inst_RAM_Word2_INIT_25,
INIT_26 => PM_Inst_RAM_Word2_INIT_26,
INIT_27 => PM_Inst_RAM_Word2_INIT_27,
INIT_28 => PM_Inst_RAM_Word2_INIT_28,
INIT_29 => PM_Inst_RAM_Word2_INIT_29,
INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word2_INIT_30,
INIT_31 => PM_Inst_RAM_Word2_INIT_31,
INIT_32 => PM_Inst_RAM_Word2_INIT_32,
INIT_33 => PM_Inst_RAM_Word2_INIT_33,
INIT_34 => PM_Inst_RAM_Word2_INIT_34,
INIT_35 => PM_Inst_RAM_Word2_INIT_35,
INIT_36 => PM_Inst_RAM_Word2_INIT_36,
INIT_37 => PM_Inst_RAM_Word2_INIT_37,
INIT_38 => PM_Inst_RAM_Word2_INIT_38,
INIT_39 => PM_Inst_RAM_Word2_INIT_39,
INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
INIT_3F => PM_Inst_RAM_Word2_INIT_3F
)
port map(
DO => RAMBlDOut(2)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(2)
);
RAM_Word3:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word3_INIT_00,
INIT_01 => PM_Inst_RAM_Word3_INIT_01,
INIT_02 => PM_Inst_RAM_Word3_INIT_02,
INIT_03 => PM_Inst_RAM_Word3_INIT_03,
INIT_04 => PM_Inst_RAM_Word3_INIT_04,
INIT_05 => PM_Inst_RAM_Word3_INIT_05,
INIT_06 => PM_Inst_RAM_Word3_INIT_06,
INIT_07 => PM_Inst_RAM_Word3_INIT_07,
INIT_08 => PM_Inst_RAM_Word3_INIT_08,
INIT_09 => PM_Inst_RAM_Word3_INIT_09,
INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
INIT_10 => PM_Inst_RAM_Word3_INIT_10,
INIT_11 => PM_Inst_RAM_Word3_INIT_11,
INIT_12 => PM_Inst_RAM_Word3_INIT_12,
INIT_13 => PM_Inst_RAM_Word3_INIT_13,
INIT_14 => PM_Inst_RAM_Word3_INIT_14,
INIT_15 => PM_Inst_RAM_Word3_INIT_15,
INIT_16 => PM_Inst_RAM_Word3_INIT_16,
INIT_17 => PM_Inst_RAM_Word3_INIT_17,
INIT_18 => PM_Inst_RAM_Word3_INIT_18,
INIT_19 => PM_Inst_RAM_Word3_INIT_19,
INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
INIT_20 => PM_Inst_RAM_Word3_INIT_20,
INIT_21 => PM_Inst_RAM_Word3_INIT_21,
INIT_22 => PM_Inst_RAM_Word3_INIT_22,
INIT_23 => PM_Inst_RAM_Word3_INIT_23,
INIT_24 => PM_Inst_RAM_Word3_INIT_24,
INIT_25 => PM_Inst_RAM_Word3_INIT_25,
INIT_26 => PM_Inst_RAM_Word3_INIT_26,
INIT_27 => PM_Inst_RAM_Word3_INIT_27,
INIT_28 => PM_Inst_RAM_Word3_INIT_28,
INIT_29 => PM_Inst_RAM_Word3_INIT_29,
INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word3_INIT_30,
INIT_31 => PM_Inst_RAM_Word3_INIT_31,
INIT_32 => PM_Inst_RAM_Word3_INIT_32,
INIT_33 => PM_Inst_RAM_Word3_INIT_33,
INIT_34 => PM_Inst_RAM_Word3_INIT_34,
INIT_35 => PM_Inst_RAM_Word3_INIT_35,
INIT_36 => PM_Inst_RAM_Word3_INIT_36,
INIT_37 => PM_Inst_RAM_Word3_INIT_37,
INIT_38 => PM_Inst_RAM_Word3_INIT_38,
INIT_39 => PM_Inst_RAM_Word3_INIT_39,
INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
INIT_3F => PM_Inst_RAM_Word3_INIT_3F
)
port map(
DO => RAMBlDOut(3)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(3)
);
RAM_Word4:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word4_INIT_00,
INIT_01 => PM_Inst_RAM_Word4_INIT_01,
INIT_02 => PM_Inst_RAM_Word4_INIT_02,
INIT_03 => PM_Inst_RAM_Word4_INIT_03,
INIT_04 => PM_Inst_RAM_Word4_INIT_04,
INIT_05 => PM_Inst_RAM_Word4_INIT_05,
INIT_06 => PM_Inst_RAM_Word4_INIT_06,
INIT_07 => PM_Inst_RAM_Word4_INIT_07,
INIT_08 => PM_Inst_RAM_Word4_INIT_08,
INIT_09 => PM_Inst_RAM_Word4_INIT_09,
INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
INIT_10 => PM_Inst_RAM_Word4_INIT_10,
INIT_11 => PM_Inst_RAM_Word4_INIT_11,
INIT_12 => PM_Inst_RAM_Word4_INIT_12,
INIT_13 => PM_Inst_RAM_Word4_INIT_13,
INIT_14 => PM_Inst_RAM_Word4_INIT_14,
INIT_15 => PM_Inst_RAM_Word4_INIT_15,
INIT_16 => PM_Inst_RAM_Word4_INIT_16,
INIT_17 => PM_Inst_RAM_Word4_INIT_17,
INIT_18 => PM_Inst_RAM_Word4_INIT_18,
INIT_19 => PM_Inst_RAM_Word4_INIT_19,
INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
INIT_20 => PM_Inst_RAM_Word4_INIT_20,
INIT_21 => PM_Inst_RAM_Word4_INIT_21,
INIT_22 => PM_Inst_RAM_Word4_INIT_22,
INIT_23 => PM_Inst_RAM_Word4_INIT_23,
INIT_24 => PM_Inst_RAM_Word4_INIT_24,
INIT_25 => PM_Inst_RAM_Word4_INIT_25,
INIT_26 => PM_Inst_RAM_Word4_INIT_26,
INIT_27 => PM_Inst_RAM_Word4_INIT_27,
INIT_28 => PM_Inst_RAM_Word4_INIT_28,
INIT_29 => PM_Inst_RAM_Word4_INIT_29,
INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word4_INIT_30,
INIT_31 => PM_Inst_RAM_Word4_INIT_31,
INIT_32 => PM_Inst_RAM_Word4_INIT_32,
INIT_33 => PM_Inst_RAM_Word4_INIT_33,
INIT_34 => PM_Inst_RAM_Word4_INIT_34,
INIT_35 => PM_Inst_RAM_Word4_INIT_35,
INIT_36 => PM_Inst_RAM_Word4_INIT_36,
INIT_37 => PM_Inst_RAM_Word4_INIT_37,
INIT_38 => PM_Inst_RAM_Word4_INIT_38,
INIT_39 => PM_Inst_RAM_Word4_INIT_39,
INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
INIT_3F => PM_Inst_RAM_Word4_INIT_3F
)
port map(
DO => RAMBlDOut(4)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(4)
);
RAM_Word5:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word5_INIT_00,
INIT_01 => PM_Inst_RAM_Word5_INIT_01,
INIT_02 => PM_Inst_RAM_Word5_INIT_02,
INIT_03 => PM_Inst_RAM_Word5_INIT_03,
INIT_04 => PM_Inst_RAM_Word5_INIT_04,
INIT_05 => PM_Inst_RAM_Word5_INIT_05,
INIT_06 => PM_Inst_RAM_Word5_INIT_06,
INIT_07 => PM_Inst_RAM_Word5_INIT_07,
INIT_08 => PM_Inst_RAM_Word5_INIT_08,
INIT_09 => PM_Inst_RAM_Word5_INIT_09,
INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
INIT_10 => PM_Inst_RAM_Word5_INIT_10,
INIT_11 => PM_Inst_RAM_Word5_INIT_11,
INIT_12 => PM_Inst_RAM_Word5_INIT_12,
INIT_13 => PM_Inst_RAM_Word5_INIT_13,
INIT_14 => PM_Inst_RAM_Word5_INIT_14,
INIT_15 => PM_Inst_RAM_Word5_INIT_15,
INIT_16 => PM_Inst_RAM_Word5_INIT_16,
INIT_17 => PM_Inst_RAM_Word5_INIT_17,
INIT_18 => PM_Inst_RAM_Word5_INIT_18,
INIT_19 => PM_Inst_RAM_Word5_INIT_19,
INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
INIT_20 => PM_Inst_RAM_Word5_INIT_20,
INIT_21 => PM_Inst_RAM_Word5_INIT_21,
INIT_22 => PM_Inst_RAM_Word5_INIT_22,
INIT_23 => PM_Inst_RAM_Word5_INIT_23,
INIT_24 => PM_Inst_RAM_Word5_INIT_24,
INIT_25 => PM_Inst_RAM_Word5_INIT_25,
INIT_26 => PM_Inst_RAM_Word5_INIT_26,
INIT_27 => PM_Inst_RAM_Word5_INIT_27,
INIT_28 => PM_Inst_RAM_Word5_INIT_28,
INIT_29 => PM_Inst_RAM_Word5_INIT_29,
INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word5_INIT_30,
INIT_31 => PM_Inst_RAM_Word5_INIT_31,
INIT_32 => PM_Inst_RAM_Word5_INIT_32,
INIT_33 => PM_Inst_RAM_Word5_INIT_33,
INIT_34 => PM_Inst_RAM_Word5_INIT_34,
INIT_35 => PM_Inst_RAM_Word5_INIT_35,
INIT_36 => PM_Inst_RAM_Word5_INIT_36,
INIT_37 => PM_Inst_RAM_Word5_INIT_37,
INIT_38 => PM_Inst_RAM_Word5_INIT_38,
INIT_39 => PM_Inst_RAM_Word5_INIT_39,
INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
INIT_3F => PM_Inst_RAM_Word5_INIT_3F
)
port map(
DO => RAMBlDOut(5)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(5)
);
RAM_Word6:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word6_INIT_00,
INIT_01 => PM_Inst_RAM_Word6_INIT_01,
INIT_02 => PM_Inst_RAM_Word6_INIT_02,
INIT_03 => PM_Inst_RAM_Word6_INIT_03,
INIT_04 => PM_Inst_RAM_Word6_INIT_04,
INIT_05 => PM_Inst_RAM_Word6_INIT_05,
INIT_06 => PM_Inst_RAM_Word6_INIT_06,
INIT_07 => PM_Inst_RAM_Word6_INIT_07,
INIT_08 => PM_Inst_RAM_Word6_INIT_08,
INIT_09 => PM_Inst_RAM_Word6_INIT_09,
INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
INIT_10 => PM_Inst_RAM_Word6_INIT_10,
INIT_11 => PM_Inst_RAM_Word6_INIT_11,
INIT_12 => PM_Inst_RAM_Word6_INIT_12,
INIT_13 => PM_Inst_RAM_Word6_INIT_13,
INIT_14 => PM_Inst_RAM_Word6_INIT_14,
INIT_15 => PM_Inst_RAM_Word6_INIT_15,
INIT_16 => PM_Inst_RAM_Word6_INIT_16,
INIT_17 => PM_Inst_RAM_Word6_INIT_17,
INIT_18 => PM_Inst_RAM_Word6_INIT_18,
INIT_19 => PM_Inst_RAM_Word6_INIT_19,
INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
INIT_20 => PM_Inst_RAM_Word6_INIT_20,
INIT_21 => PM_Inst_RAM_Word6_INIT_21,
INIT_22 => PM_Inst_RAM_Word6_INIT_22,
INIT_23 => PM_Inst_RAM_Word6_INIT_23,
INIT_24 => PM_Inst_RAM_Word6_INIT_24,
INIT_25 => PM_Inst_RAM_Word6_INIT_25,
INIT_26 => PM_Inst_RAM_Word6_INIT_26,
INIT_27 => PM_Inst_RAM_Word6_INIT_27,
INIT_28 => PM_Inst_RAM_Word6_INIT_28,
INIT_29 => PM_Inst_RAM_Word6_INIT_29,
INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word6_INIT_30,
INIT_31 => PM_Inst_RAM_Word6_INIT_31,
INIT_32 => PM_Inst_RAM_Word6_INIT_32,
INIT_33 => PM_Inst_RAM_Word6_INIT_33,
INIT_34 => PM_Inst_RAM_Word6_INIT_34,
INIT_35 => PM_Inst_RAM_Word6_INIT_35,
INIT_36 => PM_Inst_RAM_Word6_INIT_36,
INIT_37 => PM_Inst_RAM_Word6_INIT_37,
INIT_38 => PM_Inst_RAM_Word6_INIT_38,
INIT_39 => PM_Inst_RAM_Word6_INIT_39,
INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
INIT_3F => PM_Inst_RAM_Word6_INIT_3F
)
port map(
DO => RAMBlDOut(6)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(6)
);
RAM_Word7:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(7)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(7)
);
--end generate;
RAM_Word8:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(8)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(8)
);
--end generate;
RAM_Word9:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(9)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(9)
);
--end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;

81
src/AVR8/Memory/XPM16Kx16.vhd
View File

@ -1,81 +0,0 @@
--************************************************************************************************
-- 16Kx16(32 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM16Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
weh : in std_logic;
wel : in std_logic
);
end XPM16Kx16;
architecture RTL of XPM16Kx16 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEBL : std_logic_vector(2**(address'length-9)-1 downto 0);
signal WEBH : std_logic_vector(2**(address'length-9)-1 downto 0);
signal gnd : std_logic;
begin
gnd <= '0';
WEBH_Dcd:for i in WEBL'range generate
WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
end generate ;
WEBL_Dcd:for i in WEBH'range generate
WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_ByteLow:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEBL(i),
RST => gnd
);
RAM_ByteHigh:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(15 downto 8),
ADDR => address(8 downto 0),
DI => din(15 downto 8),
EN => ce,
CLK => cp2,
WE => WEBH(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;

156
src/AVR8/Memory/XPM4Kx16.vhd
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@ -1,156 +0,0 @@
--************************************************************************************************
-- 4Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok modified by Jack Gassett for use with Spartan 3E
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM4Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(11 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM4Kx16;
architecture RTL of XPM4Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C005B940C",
INIT_01 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C007E940C",
INIT_02 => X"007E940C007E940C007E940C007E940C007E940C007E940C007E940C009D940C",
INIT_03 => X"0404040404040030003600000000003200350038000000000031003700000000",
INIT_04 => X"0804020120100804020180402010080402010303030303030202020202020404",
INIT_05 => X"BFDEE0DFEFCFBE1F241100000000000000000604030000010200070000002010",
INIT_06 => X"07B136A2F3C89631920D95D8C004BF0B9503EF0FE0F3E2ECE0B0E6A0E010BFCD",
INIT_07 => X"0000940C0194940C018D940EF7E107B136AB921DC001E0B0E6A2E010BE1BF7C9",
INIT_08 => X"0151940EE0600060918000F5940EE090E080E070E0610151940EE06100609180",
INIT_09 => X"B60F920F921F95080129940EE06100609180950800F5940EE090E080E070E061",
INIT_0A => X"006791300066912093BF93AF939F938F937F936F935F934F933F932F2411920F",
INIT_0B => X"376D5F6A2F671DB11DA196022F822F932FA42FB5006A91700069915000689140",
INIT_0C => X"93A00067939000669380006A93601DB11DA196032F822F932FA42FB5576DF040",
INIT_0D => X"006293801DB11DA19601006591B0006491A00063919000629180006993B00068",
INIT_0E => X"912F913F914F915F916F917F918F919F91AF91BF006593B0006493A000639390",
INIT_0F => X"914094F8B78F2F192F082EF72EE6931F930F92FF92EF9518901F900FBE0F900F",
INIT_10 => X"006891A0006791900066918094F8B72FBF8F0069917000689160006791500066",
INIT_11 => X"90EF90FF910F911FF760071B070A06F916E80BB70BA60B951B84BF2F006991B0",
INIT_12 => X"2FE84F9F57822F932F82E0302F289508BF876081B787BF836084B78394789508",
INIT_13 => X"5AE01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE24F3F58262D9095C82FF9",
INIT_14 => X"938C2B89918C9508938C23899590918CF42923662DB095C896312DA095C84FFF",
INIT_15 => X"2FE84F9F57822F952F842D2095C82FF92FE84F9F558E2F952F84E0502F489508",
INIT_16 => X"B58FF4193023F0512322F10923332D3095C82FF52FE44F5F58462D9095C82FF9",
INIT_17 => X"96312DA095C84FFF59E81FFF0FEEE0F02FE3BD8F7D8FB58FF4193024C004778F",
INIT_18 => X"940E0121940E9508938C2B89918C9508938C23899590918CF42923662DB095C8",
INIT_19 => X"000000000000000000000000000000000000000DCFFF94F8CFFD0080940E0097",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 255
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map(
DO => RAMBlDOut(i)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;

735
src/AVR8/Memory/XPM8Kx16.vhd
View File

@ -1,735 +0,0 @@
--************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM8Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CPROGMEMSIZE downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM8Kx16;
architecture RTL of XPM8Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word0:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word0_INIT_00,
INIT_01 => PM_Inst_RAM_Word0_INIT_01,
INIT_02 => PM_Inst_RAM_Word0_INIT_02,
INIT_03 => PM_Inst_RAM_Word0_INIT_03,
INIT_04 => PM_Inst_RAM_Word0_INIT_04,
INIT_05 => PM_Inst_RAM_Word0_INIT_05,
INIT_06 => PM_Inst_RAM_Word0_INIT_06,
INIT_07 => PM_Inst_RAM_Word0_INIT_07,
INIT_08 => PM_Inst_RAM_Word0_INIT_08,
INIT_09 => PM_Inst_RAM_Word0_INIT_09,
INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
INIT_10 => PM_Inst_RAM_Word0_INIT_10,
INIT_11 => PM_Inst_RAM_Word0_INIT_11,
INIT_12 => PM_Inst_RAM_Word0_INIT_12,
INIT_13 => PM_Inst_RAM_Word0_INIT_13,
INIT_14 => PM_Inst_RAM_Word0_INIT_14,
INIT_15 => PM_Inst_RAM_Word0_INIT_15,
INIT_16 => PM_Inst_RAM_Word0_INIT_16,
INIT_17 => PM_Inst_RAM_Word0_INIT_17,
INIT_18 => PM_Inst_RAM_Word0_INIT_18,
INIT_19 => PM_Inst_RAM_Word0_INIT_19,
INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
INIT_20 => PM_Inst_RAM_Word0_INIT_20,
INIT_21 => PM_Inst_RAM_Word0_INIT_21,
INIT_22 => PM_Inst_RAM_Word0_INIT_22,
INIT_23 => PM_Inst_RAM_Word0_INIT_23,
INIT_24 => PM_Inst_RAM_Word0_INIT_24,
INIT_25 => PM_Inst_RAM_Word0_INIT_25,
INIT_26 => PM_Inst_RAM_Word0_INIT_26,
INIT_27 => PM_Inst_RAM_Word0_INIT_27,
INIT_28 => PM_Inst_RAM_Word0_INIT_28,
INIT_29 => PM_Inst_RAM_Word0_INIT_29,
INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word0_INIT_30,
INIT_31 => PM_Inst_RAM_Word0_INIT_31,
INIT_32 => PM_Inst_RAM_Word0_INIT_32,
INIT_33 => PM_Inst_RAM_Word0_INIT_33,
INIT_34 => PM_Inst_RAM_Word0_INIT_34,
INIT_35 => PM_Inst_RAM_Word0_INIT_35,
INIT_36 => PM_Inst_RAM_Word0_INIT_36,
INIT_37 => PM_Inst_RAM_Word0_INIT_37,
INIT_38 => PM_Inst_RAM_Word0_INIT_38,
INIT_39 => PM_Inst_RAM_Word0_INIT_39,
INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
INIT_3F => PM_Inst_RAM_Word0_INIT_3F
)
port map(
DO => RAMBlDOut(0)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(0)
);
RAM_Word1:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word1_INIT_00,
INIT_01 => PM_Inst_RAM_Word1_INIT_01,
INIT_02 => PM_Inst_RAM_Word1_INIT_02,
INIT_03 => PM_Inst_RAM_Word1_INIT_03,
INIT_04 => PM_Inst_RAM_Word1_INIT_04,
INIT_05 => PM_Inst_RAM_Word1_INIT_05,
INIT_06 => PM_Inst_RAM_Word1_INIT_06,
INIT_07 => PM_Inst_RAM_Word1_INIT_07,
INIT_08 => PM_Inst_RAM_Word1_INIT_08,
INIT_09 => PM_Inst_RAM_Word1_INIT_09,
INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
INIT_10 => PM_Inst_RAM_Word1_INIT_10,
INIT_11 => PM_Inst_RAM_Word1_INIT_11,
INIT_12 => PM_Inst_RAM_Word1_INIT_12,
INIT_13 => PM_Inst_RAM_Word1_INIT_13,
INIT_14 => PM_Inst_RAM_Word1_INIT_14,
INIT_15 => PM_Inst_RAM_Word1_INIT_15,
INIT_16 => PM_Inst_RAM_Word1_INIT_16,
INIT_17 => PM_Inst_RAM_Word1_INIT_17,
INIT_18 => PM_Inst_RAM_Word1_INIT_18,
INIT_19 => PM_Inst_RAM_Word1_INIT_19,
INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
INIT_20 => PM_Inst_RAM_Word1_INIT_20,
INIT_21 => PM_Inst_RAM_Word1_INIT_21,
INIT_22 => PM_Inst_RAM_Word1_INIT_22,
INIT_23 => PM_Inst_RAM_Word1_INIT_23,
INIT_24 => PM_Inst_RAM_Word1_INIT_24,
INIT_25 => PM_Inst_RAM_Word1_INIT_25,
INIT_26 => PM_Inst_RAM_Word1_INIT_26,
INIT_27 => PM_Inst_RAM_Word1_INIT_27,
INIT_28 => PM_Inst_RAM_Word1_INIT_28,
INIT_29 => PM_Inst_RAM_Word1_INIT_29,
INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word1_INIT_30,
INIT_31 => PM_Inst_RAM_Word1_INIT_31,
INIT_32 => PM_Inst_RAM_Word1_INIT_32,
INIT_33 => PM_Inst_RAM_Word1_INIT_33,
INIT_34 => PM_Inst_RAM_Word1_INIT_34,
INIT_35 => PM_Inst_RAM_Word1_INIT_35,
INIT_36 => PM_Inst_RAM_Word1_INIT_36,
INIT_37 => PM_Inst_RAM_Word1_INIT_37,
INIT_38 => PM_Inst_RAM_Word1_INIT_38,
INIT_39 => PM_Inst_RAM_Word1_INIT_39,
INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
INIT_3F => PM_Inst_RAM_Word1_INIT_3F
)
port map(
DO => RAMBlDOut(1)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(1)
);
RAM_Word2:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word2_INIT_00,
INIT_01 => PM_Inst_RAM_Word2_INIT_01,
INIT_02 => PM_Inst_RAM_Word2_INIT_02,
INIT_03 => PM_Inst_RAM_Word2_INIT_03,
INIT_04 => PM_Inst_RAM_Word2_INIT_04,
INIT_05 => PM_Inst_RAM_Word2_INIT_05,
INIT_06 => PM_Inst_RAM_Word2_INIT_06,
INIT_07 => PM_Inst_RAM_Word2_INIT_07,
INIT_08 => PM_Inst_RAM_Word2_INIT_08,
INIT_09 => PM_Inst_RAM_Word2_INIT_09,
INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
INIT_10 => PM_Inst_RAM_Word2_INIT_10,
INIT_11 => PM_Inst_RAM_Word2_INIT_11,
INIT_12 => PM_Inst_RAM_Word2_INIT_12,
INIT_13 => PM_Inst_RAM_Word2_INIT_13,
INIT_14 => PM_Inst_RAM_Word2_INIT_14,
INIT_15 => PM_Inst_RAM_Word2_INIT_15,
INIT_16 => PM_Inst_RAM_Word2_INIT_16,
INIT_17 => PM_Inst_RAM_Word2_INIT_17,
INIT_18 => PM_Inst_RAM_Word2_INIT_18,
INIT_19 => PM_Inst_RAM_Word2_INIT_19,
INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
INIT_20 => PM_Inst_RAM_Word2_INIT_20,
INIT_21 => PM_Inst_RAM_Word2_INIT_21,
INIT_22 => PM_Inst_RAM_Word2_INIT_22,
INIT_23 => PM_Inst_RAM_Word2_INIT_23,
INIT_24 => PM_Inst_RAM_Word2_INIT_24,
INIT_25 => PM_Inst_RAM_Word2_INIT_25,
INIT_26 => PM_Inst_RAM_Word2_INIT_26,
INIT_27 => PM_Inst_RAM_Word2_INIT_27,
INIT_28 => PM_Inst_RAM_Word2_INIT_28,
INIT_29 => PM_Inst_RAM_Word2_INIT_29,
INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word2_INIT_30,
INIT_31 => PM_Inst_RAM_Word2_INIT_31,
INIT_32 => PM_Inst_RAM_Word2_INIT_32,
INIT_33 => PM_Inst_RAM_Word2_INIT_33,
INIT_34 => PM_Inst_RAM_Word2_INIT_34,
INIT_35 => PM_Inst_RAM_Word2_INIT_35,
INIT_36 => PM_Inst_RAM_Word2_INIT_36,
INIT_37 => PM_Inst_RAM_Word2_INIT_37,
INIT_38 => PM_Inst_RAM_Word2_INIT_38,
INIT_39 => PM_Inst_RAM_Word2_INIT_39,
INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
INIT_3F => PM_Inst_RAM_Word2_INIT_3F
)
port map(
DO => RAMBlDOut(2)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(2)
);
RAM_Word3:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word3_INIT_00,
INIT_01 => PM_Inst_RAM_Word3_INIT_01,
INIT_02 => PM_Inst_RAM_Word3_INIT_02,
INIT_03 => PM_Inst_RAM_Word3_INIT_03,
INIT_04 => PM_Inst_RAM_Word3_INIT_04,
INIT_05 => PM_Inst_RAM_Word3_INIT_05,
INIT_06 => PM_Inst_RAM_Word3_INIT_06,
INIT_07 => PM_Inst_RAM_Word3_INIT_07,
INIT_08 => PM_Inst_RAM_Word3_INIT_08,
INIT_09 => PM_Inst_RAM_Word3_INIT_09,
INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
INIT_10 => PM_Inst_RAM_Word3_INIT_10,
INIT_11 => PM_Inst_RAM_Word3_INIT_11,
INIT_12 => PM_Inst_RAM_Word3_INIT_12,
INIT_13 => PM_Inst_RAM_Word3_INIT_13,
INIT_14 => PM_Inst_RAM_Word3_INIT_14,
INIT_15 => PM_Inst_RAM_Word3_INIT_15,
INIT_16 => PM_Inst_RAM_Word3_INIT_16,
INIT_17 => PM_Inst_RAM_Word3_INIT_17,
INIT_18 => PM_Inst_RAM_Word3_INIT_18,
INIT_19 => PM_Inst_RAM_Word3_INIT_19,
INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
INIT_20 => PM_Inst_RAM_Word3_INIT_20,
INIT_21 => PM_Inst_RAM_Word3_INIT_21,
INIT_22 => PM_Inst_RAM_Word3_INIT_22,
INIT_23 => PM_Inst_RAM_Word3_INIT_23,
INIT_24 => PM_Inst_RAM_Word3_INIT_24,
INIT_25 => PM_Inst_RAM_Word3_INIT_25,
INIT_26 => PM_Inst_RAM_Word3_INIT_26,
INIT_27 => PM_Inst_RAM_Word3_INIT_27,
INIT_28 => PM_Inst_RAM_Word3_INIT_28,
INIT_29 => PM_Inst_RAM_Word3_INIT_29,
INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word3_INIT_30,
INIT_31 => PM_Inst_RAM_Word3_INIT_31,
INIT_32 => PM_Inst_RAM_Word3_INIT_32,
INIT_33 => PM_Inst_RAM_Word3_INIT_33,
INIT_34 => PM_Inst_RAM_Word3_INIT_34,
INIT_35 => PM_Inst_RAM_Word3_INIT_35,
INIT_36 => PM_Inst_RAM_Word3_INIT_36,
INIT_37 => PM_Inst_RAM_Word3_INIT_37,
INIT_38 => PM_Inst_RAM_Word3_INIT_38,
INIT_39 => PM_Inst_RAM_Word3_INIT_39,
INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
INIT_3F => PM_Inst_RAM_Word3_INIT_3F
)
port map(
DO => RAMBlDOut(3)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(3)
);
RAM_Word4:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word4_INIT_00,
INIT_01 => PM_Inst_RAM_Word4_INIT_01,
INIT_02 => PM_Inst_RAM_Word4_INIT_02,
INIT_03 => PM_Inst_RAM_Word4_INIT_03,
INIT_04 => PM_Inst_RAM_Word4_INIT_04,
INIT_05 => PM_Inst_RAM_Word4_INIT_05,
INIT_06 => PM_Inst_RAM_Word4_INIT_06,
INIT_07 => PM_Inst_RAM_Word4_INIT_07,
INIT_08 => PM_Inst_RAM_Word4_INIT_08,
INIT_09 => PM_Inst_RAM_Word4_INIT_09,
INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
INIT_10 => PM_Inst_RAM_Word4_INIT_10,
INIT_11 => PM_Inst_RAM_Word4_INIT_11,
INIT_12 => PM_Inst_RAM_Word4_INIT_12,
INIT_13 => PM_Inst_RAM_Word4_INIT_13,
INIT_14 => PM_Inst_RAM_Word4_INIT_14,
INIT_15 => PM_Inst_RAM_Word4_INIT_15,
INIT_16 => PM_Inst_RAM_Word4_INIT_16,
INIT_17 => PM_Inst_RAM_Word4_INIT_17,
INIT_18 => PM_Inst_RAM_Word4_INIT_18,
INIT_19 => PM_Inst_RAM_Word4_INIT_19,
INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
INIT_20 => PM_Inst_RAM_Word4_INIT_20,
INIT_21 => PM_Inst_RAM_Word4_INIT_21,
INIT_22 => PM_Inst_RAM_Word4_INIT_22,
INIT_23 => PM_Inst_RAM_Word4_INIT_23,
INIT_24 => PM_Inst_RAM_Word4_INIT_24,
INIT_25 => PM_Inst_RAM_Word4_INIT_25,
INIT_26 => PM_Inst_RAM_Word4_INIT_26,
INIT_27 => PM_Inst_RAM_Word4_INIT_27,
INIT_28 => PM_Inst_RAM_Word4_INIT_28,
INIT_29 => PM_Inst_RAM_Word4_INIT_29,
INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word4_INIT_30,
INIT_31 => PM_Inst_RAM_Word4_INIT_31,
INIT_32 => PM_Inst_RAM_Word4_INIT_32,
INIT_33 => PM_Inst_RAM_Word4_INIT_33,
INIT_34 => PM_Inst_RAM_Word4_INIT_34,
INIT_35 => PM_Inst_RAM_Word4_INIT_35,
INIT_36 => PM_Inst_RAM_Word4_INIT_36,
INIT_37 => PM_Inst_RAM_Word4_INIT_37,
INIT_38 => PM_Inst_RAM_Word4_INIT_38,
INIT_39 => PM_Inst_RAM_Word4_INIT_39,
INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
INIT_3F => PM_Inst_RAM_Word4_INIT_3F
)
port map(
DO => RAMBlDOut(4)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(4)
);
RAM_Word5:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word5_INIT_00,
INIT_01 => PM_Inst_RAM_Word5_INIT_01,
INIT_02 => PM_Inst_RAM_Word5_INIT_02,
INIT_03 => PM_Inst_RAM_Word5_INIT_03,
INIT_04 => PM_Inst_RAM_Word5_INIT_04,
INIT_05 => PM_Inst_RAM_Word5_INIT_05,
INIT_06 => PM_Inst_RAM_Word5_INIT_06,
INIT_07 => PM_Inst_RAM_Word5_INIT_07,
INIT_08 => PM_Inst_RAM_Word5_INIT_08,
INIT_09 => PM_Inst_RAM_Word5_INIT_09,
INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
INIT_10 => PM_Inst_RAM_Word5_INIT_10,
INIT_11 => PM_Inst_RAM_Word5_INIT_11,
INIT_12 => PM_Inst_RAM_Word5_INIT_12,
INIT_13 => PM_Inst_RAM_Word5_INIT_13,
INIT_14 => PM_Inst_RAM_Word5_INIT_14,
INIT_15 => PM_Inst_RAM_Word5_INIT_15,
INIT_16 => PM_Inst_RAM_Word5_INIT_16,
INIT_17 => PM_Inst_RAM_Word5_INIT_17,
INIT_18 => PM_Inst_RAM_Word5_INIT_18,
INIT_19 => PM_Inst_RAM_Word5_INIT_19,
INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
INIT_20 => PM_Inst_RAM_Word5_INIT_20,
INIT_21 => PM_Inst_RAM_Word5_INIT_21,
INIT_22 => PM_Inst_RAM_Word5_INIT_22,
INIT_23 => PM_Inst_RAM_Word5_INIT_23,
INIT_24 => PM_Inst_RAM_Word5_INIT_24,
INIT_25 => PM_Inst_RAM_Word5_INIT_25,
INIT_26 => PM_Inst_RAM_Word5_INIT_26,
INIT_27 => PM_Inst_RAM_Word5_INIT_27,
INIT_28 => PM_Inst_RAM_Word5_INIT_28,
INIT_29 => PM_Inst_RAM_Word5_INIT_29,
INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word5_INIT_30,
INIT_31 => PM_Inst_RAM_Word5_INIT_31,
INIT_32 => PM_Inst_RAM_Word5_INIT_32,
INIT_33 => PM_Inst_RAM_Word5_INIT_33,
INIT_34 => PM_Inst_RAM_Word5_INIT_34,
INIT_35 => PM_Inst_RAM_Word5_INIT_35,
INIT_36 => PM_Inst_RAM_Word5_INIT_36,
INIT_37 => PM_Inst_RAM_Word5_INIT_37,
INIT_38 => PM_Inst_RAM_Word5_INIT_38,
INIT_39 => PM_Inst_RAM_Word5_INIT_39,
INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
INIT_3F => PM_Inst_RAM_Word5_INIT_3F
)
port map(
DO => RAMBlDOut(5)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(5)
);
RAM_Word6:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word6_INIT_00,
INIT_01 => PM_Inst_RAM_Word6_INIT_01,
INIT_02 => PM_Inst_RAM_Word6_INIT_02,
INIT_03 => PM_Inst_RAM_Word6_INIT_03,
INIT_04 => PM_Inst_RAM_Word6_INIT_04,
INIT_05 => PM_Inst_RAM_Word6_INIT_05,
INIT_06 => PM_Inst_RAM_Word6_INIT_06,
INIT_07 => PM_Inst_RAM_Word6_INIT_07,
INIT_08 => PM_Inst_RAM_Word6_INIT_08,
INIT_09 => PM_Inst_RAM_Word6_INIT_09,
INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
INIT_10 => PM_Inst_RAM_Word6_INIT_10,
INIT_11 => PM_Inst_RAM_Word6_INIT_11,
INIT_12 => PM_Inst_RAM_Word6_INIT_12,
INIT_13 => PM_Inst_RAM_Word6_INIT_13,
INIT_14 => PM_Inst_RAM_Word6_INIT_14,
INIT_15 => PM_Inst_RAM_Word6_INIT_15,
INIT_16 => PM_Inst_RAM_Word6_INIT_16,
INIT_17 => PM_Inst_RAM_Word6_INIT_17,
INIT_18 => PM_Inst_RAM_Word6_INIT_18,
INIT_19 => PM_Inst_RAM_Word6_INIT_19,
INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
INIT_20 => PM_Inst_RAM_Word6_INIT_20,
INIT_21 => PM_Inst_RAM_Word6_INIT_21,
INIT_22 => PM_Inst_RAM_Word6_INIT_22,
INIT_23 => PM_Inst_RAM_Word6_INIT_23,
INIT_24 => PM_Inst_RAM_Word6_INIT_24,
INIT_25 => PM_Inst_RAM_Word6_INIT_25,
INIT_26 => PM_Inst_RAM_Word6_INIT_26,
INIT_27 => PM_Inst_RAM_Word6_INIT_27,
INIT_28 => PM_Inst_RAM_Word6_INIT_28,
INIT_29 => PM_Inst_RAM_Word6_INIT_29,
INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word6_INIT_30,
INIT_31 => PM_Inst_RAM_Word6_INIT_31,
INIT_32 => PM_Inst_RAM_Word6_INIT_32,
INIT_33 => PM_Inst_RAM_Word6_INIT_33,
INIT_34 => PM_Inst_RAM_Word6_INIT_34,
INIT_35 => PM_Inst_RAM_Word6_INIT_35,
INIT_36 => PM_Inst_RAM_Word6_INIT_36,
INIT_37 => PM_Inst_RAM_Word6_INIT_37,
INIT_38 => PM_Inst_RAM_Word6_INIT_38,
INIT_39 => PM_Inst_RAM_Word6_INIT_39,
INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
INIT_3F => PM_Inst_RAM_Word6_INIT_3F
)
port map(
DO => RAMBlDOut(6)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(6)
);
RAM_Word7:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(7)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(7)
);
--end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;

826
src/AVR8/Memory/XPM9Kx16.vhd
View File

@ -1,826 +0,0 @@
--************************************************************************************************
-- 8Kx16(8 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified by Jack Gassett for use with Papilio
-- Modified 11.06.2009
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.prog_mem_init_pkg.all; -- Init file for program memory.
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM9Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end XPM9Kx16;
architecture RTL of XPM9Kx16 is
type RAMBlDOut_Type is array(2**(address'length-10)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-10)-1 downto 0);
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(1 downto 0) := "11";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 10)=i) else '0';
end generate ;
--RAM_Inst:for i in 0 to 2**(address'length-10)-1 generate
RAM_Word0:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word0_INIT_00,
INIT_01 => PM_Inst_RAM_Word0_INIT_01,
INIT_02 => PM_Inst_RAM_Word0_INIT_02,
INIT_03 => PM_Inst_RAM_Word0_INIT_03,
INIT_04 => PM_Inst_RAM_Word0_INIT_04,
INIT_05 => PM_Inst_RAM_Word0_INIT_05,
INIT_06 => PM_Inst_RAM_Word0_INIT_06,
INIT_07 => PM_Inst_RAM_Word0_INIT_07,
INIT_08 => PM_Inst_RAM_Word0_INIT_08,
INIT_09 => PM_Inst_RAM_Word0_INIT_09,
INIT_0A => PM_Inst_RAM_Word0_INIT_0A,
INIT_0B => PM_Inst_RAM_Word0_INIT_0B,
INIT_0C => PM_Inst_RAM_Word0_INIT_0C,
INIT_0D => PM_Inst_RAM_Word0_INIT_0D,
INIT_0E => PM_Inst_RAM_Word0_INIT_0E,
INIT_0F => PM_Inst_RAM_Word0_INIT_0F,
INIT_10 => PM_Inst_RAM_Word0_INIT_10,
INIT_11 => PM_Inst_RAM_Word0_INIT_11,
INIT_12 => PM_Inst_RAM_Word0_INIT_12,
INIT_13 => PM_Inst_RAM_Word0_INIT_13,
INIT_14 => PM_Inst_RAM_Word0_INIT_14,
INIT_15 => PM_Inst_RAM_Word0_INIT_15,
INIT_16 => PM_Inst_RAM_Word0_INIT_16,
INIT_17 => PM_Inst_RAM_Word0_INIT_17,
INIT_18 => PM_Inst_RAM_Word0_INIT_18,
INIT_19 => PM_Inst_RAM_Word0_INIT_19,
INIT_1A => PM_Inst_RAM_Word0_INIT_1A,
INIT_1B => PM_Inst_RAM_Word0_INIT_1B,
INIT_1C => PM_Inst_RAM_Word0_INIT_1C,
INIT_1D => PM_Inst_RAM_Word0_INIT_1D,
INIT_1E => PM_Inst_RAM_Word0_INIT_1E,
INIT_1F => PM_Inst_RAM_Word0_INIT_1F,
INIT_20 => PM_Inst_RAM_Word0_INIT_20,
INIT_21 => PM_Inst_RAM_Word0_INIT_21,
INIT_22 => PM_Inst_RAM_Word0_INIT_22,
INIT_23 => PM_Inst_RAM_Word0_INIT_23,
INIT_24 => PM_Inst_RAM_Word0_INIT_24,
INIT_25 => PM_Inst_RAM_Word0_INIT_25,
INIT_26 => PM_Inst_RAM_Word0_INIT_26,
INIT_27 => PM_Inst_RAM_Word0_INIT_27,
INIT_28 => PM_Inst_RAM_Word0_INIT_28,
INIT_29 => PM_Inst_RAM_Word0_INIT_29,
INIT_2A => PM_Inst_RAM_Word0_INIT_2A,
INIT_2B => PM_Inst_RAM_Word0_INIT_2B,
INIT_2C => PM_Inst_RAM_Word0_INIT_2C,
INIT_2D => PM_Inst_RAM_Word0_INIT_2D,
INIT_2E => PM_Inst_RAM_Word0_INIT_2E,
INIT_2F => PM_Inst_RAM_Word0_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word0_INIT_30,
INIT_31 => PM_Inst_RAM_Word0_INIT_31,
INIT_32 => PM_Inst_RAM_Word0_INIT_32,
INIT_33 => PM_Inst_RAM_Word0_INIT_33,
INIT_34 => PM_Inst_RAM_Word0_INIT_34,
INIT_35 => PM_Inst_RAM_Word0_INIT_35,
INIT_36 => PM_Inst_RAM_Word0_INIT_36,
INIT_37 => PM_Inst_RAM_Word0_INIT_37,
INIT_38 => PM_Inst_RAM_Word0_INIT_38,
INIT_39 => PM_Inst_RAM_Word0_INIT_39,
INIT_3A => PM_Inst_RAM_Word0_INIT_3A,
INIT_3B => PM_Inst_RAM_Word0_INIT_3B,
INIT_3C => PM_Inst_RAM_Word0_INIT_3C,
INIT_3D => PM_Inst_RAM_Word0_INIT_3D,
INIT_3E => PM_Inst_RAM_Word0_INIT_3E,
INIT_3F => PM_Inst_RAM_Word0_INIT_3F
)
port map(
DO => RAMBlDOut(0)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(0)
);
RAM_Word1:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word1_INIT_00,
INIT_01 => PM_Inst_RAM_Word1_INIT_01,
INIT_02 => PM_Inst_RAM_Word1_INIT_02,
INIT_03 => PM_Inst_RAM_Word1_INIT_03,
INIT_04 => PM_Inst_RAM_Word1_INIT_04,
INIT_05 => PM_Inst_RAM_Word1_INIT_05,
INIT_06 => PM_Inst_RAM_Word1_INIT_06,
INIT_07 => PM_Inst_RAM_Word1_INIT_07,
INIT_08 => PM_Inst_RAM_Word1_INIT_08,
INIT_09 => PM_Inst_RAM_Word1_INIT_09,
INIT_0A => PM_Inst_RAM_Word1_INIT_0A,
INIT_0B => PM_Inst_RAM_Word1_INIT_0B,
INIT_0C => PM_Inst_RAM_Word1_INIT_0C,
INIT_0D => PM_Inst_RAM_Word1_INIT_0D,
INIT_0E => PM_Inst_RAM_Word1_INIT_0E,
INIT_0F => PM_Inst_RAM_Word1_INIT_0F,
INIT_10 => PM_Inst_RAM_Word1_INIT_10,
INIT_11 => PM_Inst_RAM_Word1_INIT_11,
INIT_12 => PM_Inst_RAM_Word1_INIT_12,
INIT_13 => PM_Inst_RAM_Word1_INIT_13,
INIT_14 => PM_Inst_RAM_Word1_INIT_14,
INIT_15 => PM_Inst_RAM_Word1_INIT_15,
INIT_16 => PM_Inst_RAM_Word1_INIT_16,
INIT_17 => PM_Inst_RAM_Word1_INIT_17,
INIT_18 => PM_Inst_RAM_Word1_INIT_18,
INIT_19 => PM_Inst_RAM_Word1_INIT_19,
INIT_1A => PM_Inst_RAM_Word1_INIT_1A,
INIT_1B => PM_Inst_RAM_Word1_INIT_1B,
INIT_1C => PM_Inst_RAM_Word1_INIT_1C,
INIT_1D => PM_Inst_RAM_Word1_INIT_1D,
INIT_1E => PM_Inst_RAM_Word1_INIT_1E,
INIT_1F => PM_Inst_RAM_Word1_INIT_1F,
INIT_20 => PM_Inst_RAM_Word1_INIT_20,
INIT_21 => PM_Inst_RAM_Word1_INIT_21,
INIT_22 => PM_Inst_RAM_Word1_INIT_22,
INIT_23 => PM_Inst_RAM_Word1_INIT_23,
INIT_24 => PM_Inst_RAM_Word1_INIT_24,
INIT_25 => PM_Inst_RAM_Word1_INIT_25,
INIT_26 => PM_Inst_RAM_Word1_INIT_26,
INIT_27 => PM_Inst_RAM_Word1_INIT_27,
INIT_28 => PM_Inst_RAM_Word1_INIT_28,
INIT_29 => PM_Inst_RAM_Word1_INIT_29,
INIT_2A => PM_Inst_RAM_Word1_INIT_2A,
INIT_2B => PM_Inst_RAM_Word1_INIT_2B,
INIT_2C => PM_Inst_RAM_Word1_INIT_2C,
INIT_2D => PM_Inst_RAM_Word1_INIT_2D,
INIT_2E => PM_Inst_RAM_Word1_INIT_2E,
INIT_2F => PM_Inst_RAM_Word1_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word1_INIT_30,
INIT_31 => PM_Inst_RAM_Word1_INIT_31,
INIT_32 => PM_Inst_RAM_Word1_INIT_32,
INIT_33 => PM_Inst_RAM_Word1_INIT_33,
INIT_34 => PM_Inst_RAM_Word1_INIT_34,
INIT_35 => PM_Inst_RAM_Word1_INIT_35,
INIT_36 => PM_Inst_RAM_Word1_INIT_36,
INIT_37 => PM_Inst_RAM_Word1_INIT_37,
INIT_38 => PM_Inst_RAM_Word1_INIT_38,
INIT_39 => PM_Inst_RAM_Word1_INIT_39,
INIT_3A => PM_Inst_RAM_Word1_INIT_3A,
INIT_3B => PM_Inst_RAM_Word1_INIT_3B,
INIT_3C => PM_Inst_RAM_Word1_INIT_3C,
INIT_3D => PM_Inst_RAM_Word1_INIT_3D,
INIT_3E => PM_Inst_RAM_Word1_INIT_3E,
INIT_3F => PM_Inst_RAM_Word1_INIT_3F
)
port map(
DO => RAMBlDOut(1)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(1)
);
RAM_Word2:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word2_INIT_00,
INIT_01 => PM_Inst_RAM_Word2_INIT_01,
INIT_02 => PM_Inst_RAM_Word2_INIT_02,
INIT_03 => PM_Inst_RAM_Word2_INIT_03,
INIT_04 => PM_Inst_RAM_Word2_INIT_04,
INIT_05 => PM_Inst_RAM_Word2_INIT_05,
INIT_06 => PM_Inst_RAM_Word2_INIT_06,
INIT_07 => PM_Inst_RAM_Word2_INIT_07,
INIT_08 => PM_Inst_RAM_Word2_INIT_08,
INIT_09 => PM_Inst_RAM_Word2_INIT_09,
INIT_0A => PM_Inst_RAM_Word2_INIT_0A,
INIT_0B => PM_Inst_RAM_Word2_INIT_0B,
INIT_0C => PM_Inst_RAM_Word2_INIT_0C,
INIT_0D => PM_Inst_RAM_Word2_INIT_0D,
INIT_0E => PM_Inst_RAM_Word2_INIT_0E,
INIT_0F => PM_Inst_RAM_Word2_INIT_0F,
INIT_10 => PM_Inst_RAM_Word2_INIT_10,
INIT_11 => PM_Inst_RAM_Word2_INIT_11,
INIT_12 => PM_Inst_RAM_Word2_INIT_12,
INIT_13 => PM_Inst_RAM_Word2_INIT_13,
INIT_14 => PM_Inst_RAM_Word2_INIT_14,
INIT_15 => PM_Inst_RAM_Word2_INIT_15,
INIT_16 => PM_Inst_RAM_Word2_INIT_16,
INIT_17 => PM_Inst_RAM_Word2_INIT_17,
INIT_18 => PM_Inst_RAM_Word2_INIT_18,
INIT_19 => PM_Inst_RAM_Word2_INIT_19,
INIT_1A => PM_Inst_RAM_Word2_INIT_1A,
INIT_1B => PM_Inst_RAM_Word2_INIT_1B,
INIT_1C => PM_Inst_RAM_Word2_INIT_1C,
INIT_1D => PM_Inst_RAM_Word2_INIT_1D,
INIT_1E => PM_Inst_RAM_Word2_INIT_1E,
INIT_1F => PM_Inst_RAM_Word2_INIT_1F,
INIT_20 => PM_Inst_RAM_Word2_INIT_20,
INIT_21 => PM_Inst_RAM_Word2_INIT_21,
INIT_22 => PM_Inst_RAM_Word2_INIT_22,
INIT_23 => PM_Inst_RAM_Word2_INIT_23,
INIT_24 => PM_Inst_RAM_Word2_INIT_24,
INIT_25 => PM_Inst_RAM_Word2_INIT_25,
INIT_26 => PM_Inst_RAM_Word2_INIT_26,
INIT_27 => PM_Inst_RAM_Word2_INIT_27,
INIT_28 => PM_Inst_RAM_Word2_INIT_28,
INIT_29 => PM_Inst_RAM_Word2_INIT_29,
INIT_2A => PM_Inst_RAM_Word2_INIT_2A,
INIT_2B => PM_Inst_RAM_Word2_INIT_2B,
INIT_2C => PM_Inst_RAM_Word2_INIT_2C,
INIT_2D => PM_Inst_RAM_Word2_INIT_2D,
INIT_2E => PM_Inst_RAM_Word2_INIT_2E,
INIT_2F => PM_Inst_RAM_Word2_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word2_INIT_30,
INIT_31 => PM_Inst_RAM_Word2_INIT_31,
INIT_32 => PM_Inst_RAM_Word2_INIT_32,
INIT_33 => PM_Inst_RAM_Word2_INIT_33,
INIT_34 => PM_Inst_RAM_Word2_INIT_34,
INIT_35 => PM_Inst_RAM_Word2_INIT_35,
INIT_36 => PM_Inst_RAM_Word2_INIT_36,
INIT_37 => PM_Inst_RAM_Word2_INIT_37,
INIT_38 => PM_Inst_RAM_Word2_INIT_38,
INIT_39 => PM_Inst_RAM_Word2_INIT_39,
INIT_3A => PM_Inst_RAM_Word2_INIT_3A,
INIT_3B => PM_Inst_RAM_Word2_INIT_3B,
INIT_3C => PM_Inst_RAM_Word2_INIT_3C,
INIT_3D => PM_Inst_RAM_Word2_INIT_3D,
INIT_3E => PM_Inst_RAM_Word2_INIT_3E,
INIT_3F => PM_Inst_RAM_Word2_INIT_3F
)
port map(
DO => RAMBlDOut(2)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(2)
);
RAM_Word3:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word3_INIT_00,
INIT_01 => PM_Inst_RAM_Word3_INIT_01,
INIT_02 => PM_Inst_RAM_Word3_INIT_02,
INIT_03 => PM_Inst_RAM_Word3_INIT_03,
INIT_04 => PM_Inst_RAM_Word3_INIT_04,
INIT_05 => PM_Inst_RAM_Word3_INIT_05,
INIT_06 => PM_Inst_RAM_Word3_INIT_06,
INIT_07 => PM_Inst_RAM_Word3_INIT_07,
INIT_08 => PM_Inst_RAM_Word3_INIT_08,
INIT_09 => PM_Inst_RAM_Word3_INIT_09,
INIT_0A => PM_Inst_RAM_Word3_INIT_0A,
INIT_0B => PM_Inst_RAM_Word3_INIT_0B,
INIT_0C => PM_Inst_RAM_Word3_INIT_0C,
INIT_0D => PM_Inst_RAM_Word3_INIT_0D,
INIT_0E => PM_Inst_RAM_Word3_INIT_0E,
INIT_0F => PM_Inst_RAM_Word3_INIT_0F,
INIT_10 => PM_Inst_RAM_Word3_INIT_10,
INIT_11 => PM_Inst_RAM_Word3_INIT_11,
INIT_12 => PM_Inst_RAM_Word3_INIT_12,
INIT_13 => PM_Inst_RAM_Word3_INIT_13,
INIT_14 => PM_Inst_RAM_Word3_INIT_14,
INIT_15 => PM_Inst_RAM_Word3_INIT_15,
INIT_16 => PM_Inst_RAM_Word3_INIT_16,
INIT_17 => PM_Inst_RAM_Word3_INIT_17,
INIT_18 => PM_Inst_RAM_Word3_INIT_18,
INIT_19 => PM_Inst_RAM_Word3_INIT_19,
INIT_1A => PM_Inst_RAM_Word3_INIT_1A,
INIT_1B => PM_Inst_RAM_Word3_INIT_1B,
INIT_1C => PM_Inst_RAM_Word3_INIT_1C,
INIT_1D => PM_Inst_RAM_Word3_INIT_1D,
INIT_1E => PM_Inst_RAM_Word3_INIT_1E,
INIT_1F => PM_Inst_RAM_Word3_INIT_1F,
INIT_20 => PM_Inst_RAM_Word3_INIT_20,
INIT_21 => PM_Inst_RAM_Word3_INIT_21,
INIT_22 => PM_Inst_RAM_Word3_INIT_22,
INIT_23 => PM_Inst_RAM_Word3_INIT_23,
INIT_24 => PM_Inst_RAM_Word3_INIT_24,
INIT_25 => PM_Inst_RAM_Word3_INIT_25,
INIT_26 => PM_Inst_RAM_Word3_INIT_26,
INIT_27 => PM_Inst_RAM_Word3_INIT_27,
INIT_28 => PM_Inst_RAM_Word3_INIT_28,
INIT_29 => PM_Inst_RAM_Word3_INIT_29,
INIT_2A => PM_Inst_RAM_Word3_INIT_2A,
INIT_2B => PM_Inst_RAM_Word3_INIT_2B,
INIT_2C => PM_Inst_RAM_Word3_INIT_2C,
INIT_2D => PM_Inst_RAM_Word3_INIT_2D,
INIT_2E => PM_Inst_RAM_Word3_INIT_2E,
INIT_2F => PM_Inst_RAM_Word3_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word3_INIT_30,
INIT_31 => PM_Inst_RAM_Word3_INIT_31,
INIT_32 => PM_Inst_RAM_Word3_INIT_32,
INIT_33 => PM_Inst_RAM_Word3_INIT_33,
INIT_34 => PM_Inst_RAM_Word3_INIT_34,
INIT_35 => PM_Inst_RAM_Word3_INIT_35,
INIT_36 => PM_Inst_RAM_Word3_INIT_36,
INIT_37 => PM_Inst_RAM_Word3_INIT_37,
INIT_38 => PM_Inst_RAM_Word3_INIT_38,
INIT_39 => PM_Inst_RAM_Word3_INIT_39,
INIT_3A => PM_Inst_RAM_Word3_INIT_3A,
INIT_3B => PM_Inst_RAM_Word3_INIT_3B,
INIT_3C => PM_Inst_RAM_Word3_INIT_3C,
INIT_3D => PM_Inst_RAM_Word3_INIT_3D,
INIT_3E => PM_Inst_RAM_Word3_INIT_3E,
INIT_3F => PM_Inst_RAM_Word3_INIT_3F
)
port map(
DO => RAMBlDOut(3)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(3)
);
RAM_Word4:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word4_INIT_00,
INIT_01 => PM_Inst_RAM_Word4_INIT_01,
INIT_02 => PM_Inst_RAM_Word4_INIT_02,
INIT_03 => PM_Inst_RAM_Word4_INIT_03,
INIT_04 => PM_Inst_RAM_Word4_INIT_04,
INIT_05 => PM_Inst_RAM_Word4_INIT_05,
INIT_06 => PM_Inst_RAM_Word4_INIT_06,
INIT_07 => PM_Inst_RAM_Word4_INIT_07,
INIT_08 => PM_Inst_RAM_Word4_INIT_08,
INIT_09 => PM_Inst_RAM_Word4_INIT_09,
INIT_0A => PM_Inst_RAM_Word4_INIT_0A,
INIT_0B => PM_Inst_RAM_Word4_INIT_0B,
INIT_0C => PM_Inst_RAM_Word4_INIT_0C,
INIT_0D => PM_Inst_RAM_Word4_INIT_0D,
INIT_0E => PM_Inst_RAM_Word4_INIT_0E,
INIT_0F => PM_Inst_RAM_Word4_INIT_0F,
INIT_10 => PM_Inst_RAM_Word4_INIT_10,
INIT_11 => PM_Inst_RAM_Word4_INIT_11,
INIT_12 => PM_Inst_RAM_Word4_INIT_12,
INIT_13 => PM_Inst_RAM_Word4_INIT_13,
INIT_14 => PM_Inst_RAM_Word4_INIT_14,
INIT_15 => PM_Inst_RAM_Word4_INIT_15,
INIT_16 => PM_Inst_RAM_Word4_INIT_16,
INIT_17 => PM_Inst_RAM_Word4_INIT_17,
INIT_18 => PM_Inst_RAM_Word4_INIT_18,
INIT_19 => PM_Inst_RAM_Word4_INIT_19,
INIT_1A => PM_Inst_RAM_Word4_INIT_1A,
INIT_1B => PM_Inst_RAM_Word4_INIT_1B,
INIT_1C => PM_Inst_RAM_Word4_INIT_1C,
INIT_1D => PM_Inst_RAM_Word4_INIT_1D,
INIT_1E => PM_Inst_RAM_Word4_INIT_1E,
INIT_1F => PM_Inst_RAM_Word4_INIT_1F,
INIT_20 => PM_Inst_RAM_Word4_INIT_20,
INIT_21 => PM_Inst_RAM_Word4_INIT_21,
INIT_22 => PM_Inst_RAM_Word4_INIT_22,
INIT_23 => PM_Inst_RAM_Word4_INIT_23,
INIT_24 => PM_Inst_RAM_Word4_INIT_24,
INIT_25 => PM_Inst_RAM_Word4_INIT_25,
INIT_26 => PM_Inst_RAM_Word4_INIT_26,
INIT_27 => PM_Inst_RAM_Word4_INIT_27,
INIT_28 => PM_Inst_RAM_Word4_INIT_28,
INIT_29 => PM_Inst_RAM_Word4_INIT_29,
INIT_2A => PM_Inst_RAM_Word4_INIT_2A,
INIT_2B => PM_Inst_RAM_Word4_INIT_2B,
INIT_2C => PM_Inst_RAM_Word4_INIT_2C,
INIT_2D => PM_Inst_RAM_Word4_INIT_2D,
INIT_2E => PM_Inst_RAM_Word4_INIT_2E,
INIT_2F => PM_Inst_RAM_Word4_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word4_INIT_30,
INIT_31 => PM_Inst_RAM_Word4_INIT_31,
INIT_32 => PM_Inst_RAM_Word4_INIT_32,
INIT_33 => PM_Inst_RAM_Word4_INIT_33,
INIT_34 => PM_Inst_RAM_Word4_INIT_34,
INIT_35 => PM_Inst_RAM_Word4_INIT_35,
INIT_36 => PM_Inst_RAM_Word4_INIT_36,
INIT_37 => PM_Inst_RAM_Word4_INIT_37,
INIT_38 => PM_Inst_RAM_Word4_INIT_38,
INIT_39 => PM_Inst_RAM_Word4_INIT_39,
INIT_3A => PM_Inst_RAM_Word4_INIT_3A,
INIT_3B => PM_Inst_RAM_Word4_INIT_3B,
INIT_3C => PM_Inst_RAM_Word4_INIT_3C,
INIT_3D => PM_Inst_RAM_Word4_INIT_3D,
INIT_3E => PM_Inst_RAM_Word4_INIT_3E,
INIT_3F => PM_Inst_RAM_Word4_INIT_3F
)
port map(
DO => RAMBlDOut(4)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(4)
);
RAM_Word5:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word5_INIT_00,
INIT_01 => PM_Inst_RAM_Word5_INIT_01,
INIT_02 => PM_Inst_RAM_Word5_INIT_02,
INIT_03 => PM_Inst_RAM_Word5_INIT_03,
INIT_04 => PM_Inst_RAM_Word5_INIT_04,
INIT_05 => PM_Inst_RAM_Word5_INIT_05,
INIT_06 => PM_Inst_RAM_Word5_INIT_06,
INIT_07 => PM_Inst_RAM_Word5_INIT_07,
INIT_08 => PM_Inst_RAM_Word5_INIT_08,
INIT_09 => PM_Inst_RAM_Word5_INIT_09,
INIT_0A => PM_Inst_RAM_Word5_INIT_0A,
INIT_0B => PM_Inst_RAM_Word5_INIT_0B,
INIT_0C => PM_Inst_RAM_Word5_INIT_0C,
INIT_0D => PM_Inst_RAM_Word5_INIT_0D,
INIT_0E => PM_Inst_RAM_Word5_INIT_0E,
INIT_0F => PM_Inst_RAM_Word5_INIT_0F,
INIT_10 => PM_Inst_RAM_Word5_INIT_10,
INIT_11 => PM_Inst_RAM_Word5_INIT_11,
INIT_12 => PM_Inst_RAM_Word5_INIT_12,
INIT_13 => PM_Inst_RAM_Word5_INIT_13,
INIT_14 => PM_Inst_RAM_Word5_INIT_14,
INIT_15 => PM_Inst_RAM_Word5_INIT_15,
INIT_16 => PM_Inst_RAM_Word5_INIT_16,
INIT_17 => PM_Inst_RAM_Word5_INIT_17,
INIT_18 => PM_Inst_RAM_Word5_INIT_18,
INIT_19 => PM_Inst_RAM_Word5_INIT_19,
INIT_1A => PM_Inst_RAM_Word5_INIT_1A,
INIT_1B => PM_Inst_RAM_Word5_INIT_1B,
INIT_1C => PM_Inst_RAM_Word5_INIT_1C,
INIT_1D => PM_Inst_RAM_Word5_INIT_1D,
INIT_1E => PM_Inst_RAM_Word5_INIT_1E,
INIT_1F => PM_Inst_RAM_Word5_INIT_1F,
INIT_20 => PM_Inst_RAM_Word5_INIT_20,
INIT_21 => PM_Inst_RAM_Word5_INIT_21,
INIT_22 => PM_Inst_RAM_Word5_INIT_22,
INIT_23 => PM_Inst_RAM_Word5_INIT_23,
INIT_24 => PM_Inst_RAM_Word5_INIT_24,
INIT_25 => PM_Inst_RAM_Word5_INIT_25,
INIT_26 => PM_Inst_RAM_Word5_INIT_26,
INIT_27 => PM_Inst_RAM_Word5_INIT_27,
INIT_28 => PM_Inst_RAM_Word5_INIT_28,
INIT_29 => PM_Inst_RAM_Word5_INIT_29,
INIT_2A => PM_Inst_RAM_Word5_INIT_2A,
INIT_2B => PM_Inst_RAM_Word5_INIT_2B,
INIT_2C => PM_Inst_RAM_Word5_INIT_2C,
INIT_2D => PM_Inst_RAM_Word5_INIT_2D,
INIT_2E => PM_Inst_RAM_Word5_INIT_2E,
INIT_2F => PM_Inst_RAM_Word5_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word5_INIT_30,
INIT_31 => PM_Inst_RAM_Word5_INIT_31,
INIT_32 => PM_Inst_RAM_Word5_INIT_32,
INIT_33 => PM_Inst_RAM_Word5_INIT_33,
INIT_34 => PM_Inst_RAM_Word5_INIT_34,
INIT_35 => PM_Inst_RAM_Word5_INIT_35,
INIT_36 => PM_Inst_RAM_Word5_INIT_36,
INIT_37 => PM_Inst_RAM_Word5_INIT_37,
INIT_38 => PM_Inst_RAM_Word5_INIT_38,
INIT_39 => PM_Inst_RAM_Word5_INIT_39,
INIT_3A => PM_Inst_RAM_Word5_INIT_3A,
INIT_3B => PM_Inst_RAM_Word5_INIT_3B,
INIT_3C => PM_Inst_RAM_Word5_INIT_3C,
INIT_3D => PM_Inst_RAM_Word5_INIT_3D,
INIT_3E => PM_Inst_RAM_Word5_INIT_3E,
INIT_3F => PM_Inst_RAM_Word5_INIT_3F
)
port map(
DO => RAMBlDOut(5)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(5)
);
RAM_Word6:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word6_INIT_00,
INIT_01 => PM_Inst_RAM_Word6_INIT_01,
INIT_02 => PM_Inst_RAM_Word6_INIT_02,
INIT_03 => PM_Inst_RAM_Word6_INIT_03,
INIT_04 => PM_Inst_RAM_Word6_INIT_04,
INIT_05 => PM_Inst_RAM_Word6_INIT_05,
INIT_06 => PM_Inst_RAM_Word6_INIT_06,
INIT_07 => PM_Inst_RAM_Word6_INIT_07,
INIT_08 => PM_Inst_RAM_Word6_INIT_08,
INIT_09 => PM_Inst_RAM_Word6_INIT_09,
INIT_0A => PM_Inst_RAM_Word6_INIT_0A,
INIT_0B => PM_Inst_RAM_Word6_INIT_0B,
INIT_0C => PM_Inst_RAM_Word6_INIT_0C,
INIT_0D => PM_Inst_RAM_Word6_INIT_0D,
INIT_0E => PM_Inst_RAM_Word6_INIT_0E,
INIT_0F => PM_Inst_RAM_Word6_INIT_0F,
INIT_10 => PM_Inst_RAM_Word6_INIT_10,
INIT_11 => PM_Inst_RAM_Word6_INIT_11,
INIT_12 => PM_Inst_RAM_Word6_INIT_12,
INIT_13 => PM_Inst_RAM_Word6_INIT_13,
INIT_14 => PM_Inst_RAM_Word6_INIT_14,
INIT_15 => PM_Inst_RAM_Word6_INIT_15,
INIT_16 => PM_Inst_RAM_Word6_INIT_16,
INIT_17 => PM_Inst_RAM_Word6_INIT_17,
INIT_18 => PM_Inst_RAM_Word6_INIT_18,
INIT_19 => PM_Inst_RAM_Word6_INIT_19,
INIT_1A => PM_Inst_RAM_Word6_INIT_1A,
INIT_1B => PM_Inst_RAM_Word6_INIT_1B,
INIT_1C => PM_Inst_RAM_Word6_INIT_1C,
INIT_1D => PM_Inst_RAM_Word6_INIT_1D,
INIT_1E => PM_Inst_RAM_Word6_INIT_1E,
INIT_1F => PM_Inst_RAM_Word6_INIT_1F,
INIT_20 => PM_Inst_RAM_Word6_INIT_20,
INIT_21 => PM_Inst_RAM_Word6_INIT_21,
INIT_22 => PM_Inst_RAM_Word6_INIT_22,
INIT_23 => PM_Inst_RAM_Word6_INIT_23,
INIT_24 => PM_Inst_RAM_Word6_INIT_24,
INIT_25 => PM_Inst_RAM_Word6_INIT_25,
INIT_26 => PM_Inst_RAM_Word6_INIT_26,
INIT_27 => PM_Inst_RAM_Word6_INIT_27,
INIT_28 => PM_Inst_RAM_Word6_INIT_28,
INIT_29 => PM_Inst_RAM_Word6_INIT_29,
INIT_2A => PM_Inst_RAM_Word6_INIT_2A,
INIT_2B => PM_Inst_RAM_Word6_INIT_2B,
INIT_2C => PM_Inst_RAM_Word6_INIT_2C,
INIT_2D => PM_Inst_RAM_Word6_INIT_2D,
INIT_2E => PM_Inst_RAM_Word6_INIT_2E,
INIT_2F => PM_Inst_RAM_Word6_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word6_INIT_30,
INIT_31 => PM_Inst_RAM_Word6_INIT_31,
INIT_32 => PM_Inst_RAM_Word6_INIT_32,
INIT_33 => PM_Inst_RAM_Word6_INIT_33,
INIT_34 => PM_Inst_RAM_Word6_INIT_34,
INIT_35 => PM_Inst_RAM_Word6_INIT_35,
INIT_36 => PM_Inst_RAM_Word6_INIT_36,
INIT_37 => PM_Inst_RAM_Word6_INIT_37,
INIT_38 => PM_Inst_RAM_Word6_INIT_38,
INIT_39 => PM_Inst_RAM_Word6_INIT_39,
INIT_3A => PM_Inst_RAM_Word6_INIT_3A,
INIT_3B => PM_Inst_RAM_Word6_INIT_3B,
INIT_3C => PM_Inst_RAM_Word6_INIT_3C,
INIT_3D => PM_Inst_RAM_Word6_INIT_3D,
INIT_3E => PM_Inst_RAM_Word6_INIT_3E,
INIT_3F => PM_Inst_RAM_Word6_INIT_3F
)
port map(
DO => RAMBlDOut(6)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(6)
);
RAM_Word7:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(7)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(7)
);
--end generate;
RAM_Word8:component RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => PM_Inst_RAM_Word7_INIT_00,
INIT_01 => PM_Inst_RAM_Word7_INIT_01,
INIT_02 => PM_Inst_RAM_Word7_INIT_02,
INIT_03 => PM_Inst_RAM_Word7_INIT_03,
INIT_04 => PM_Inst_RAM_Word7_INIT_04,
INIT_05 => PM_Inst_RAM_Word7_INIT_05,
INIT_06 => PM_Inst_RAM_Word7_INIT_06,
INIT_07 => PM_Inst_RAM_Word7_INIT_07,
INIT_08 => PM_Inst_RAM_Word7_INIT_08,
INIT_09 => PM_Inst_RAM_Word7_INIT_09,
INIT_0A => PM_Inst_RAM_Word7_INIT_0A,
INIT_0B => PM_Inst_RAM_Word7_INIT_0B,
INIT_0C => PM_Inst_RAM_Word7_INIT_0C,
INIT_0D => PM_Inst_RAM_Word7_INIT_0D,
INIT_0E => PM_Inst_RAM_Word7_INIT_0E,
INIT_0F => PM_Inst_RAM_Word7_INIT_0F,
INIT_10 => PM_Inst_RAM_Word7_INIT_10,
INIT_11 => PM_Inst_RAM_Word7_INIT_11,
INIT_12 => PM_Inst_RAM_Word7_INIT_12,
INIT_13 => PM_Inst_RAM_Word7_INIT_13,
INIT_14 => PM_Inst_RAM_Word7_INIT_14,
INIT_15 => PM_Inst_RAM_Word7_INIT_15,
INIT_16 => PM_Inst_RAM_Word7_INIT_16,
INIT_17 => PM_Inst_RAM_Word7_INIT_17,
INIT_18 => PM_Inst_RAM_Word7_INIT_18,
INIT_19 => PM_Inst_RAM_Word7_INIT_19,
INIT_1A => PM_Inst_RAM_Word7_INIT_1A,
INIT_1B => PM_Inst_RAM_Word7_INIT_1B,
INIT_1C => PM_Inst_RAM_Word7_INIT_1C,
INIT_1D => PM_Inst_RAM_Word7_INIT_1D,
INIT_1E => PM_Inst_RAM_Word7_INIT_1E,
INIT_1F => PM_Inst_RAM_Word7_INIT_1F,
INIT_20 => PM_Inst_RAM_Word7_INIT_20,
INIT_21 => PM_Inst_RAM_Word7_INIT_21,
INIT_22 => PM_Inst_RAM_Word7_INIT_22,
INIT_23 => PM_Inst_RAM_Word7_INIT_23,
INIT_24 => PM_Inst_RAM_Word7_INIT_24,
INIT_25 => PM_Inst_RAM_Word7_INIT_25,
INIT_26 => PM_Inst_RAM_Word7_INIT_26,
INIT_27 => PM_Inst_RAM_Word7_INIT_27,
INIT_28 => PM_Inst_RAM_Word7_INIT_28,
INIT_29 => PM_Inst_RAM_Word7_INIT_29,
INIT_2A => PM_Inst_RAM_Word7_INIT_2A,
INIT_2B => PM_Inst_RAM_Word7_INIT_2B,
INIT_2C => PM_Inst_RAM_Word7_INIT_2C,
INIT_2D => PM_Inst_RAM_Word7_INIT_2D,
INIT_2E => PM_Inst_RAM_Word7_INIT_2E,
INIT_2F => PM_Inst_RAM_Word7_INIT_2F,
-- Address 768 to 1023
INIT_30 => PM_Inst_RAM_Word7_INIT_30,
INIT_31 => PM_Inst_RAM_Word7_INIT_31,
INIT_32 => PM_Inst_RAM_Word7_INIT_32,
INIT_33 => PM_Inst_RAM_Word7_INIT_33,
INIT_34 => PM_Inst_RAM_Word7_INIT_34,
INIT_35 => PM_Inst_RAM_Word7_INIT_35,
INIT_36 => PM_Inst_RAM_Word7_INIT_36,
INIT_37 => PM_Inst_RAM_Word7_INIT_37,
INIT_38 => PM_Inst_RAM_Word7_INIT_38,
INIT_39 => PM_Inst_RAM_Word7_INIT_39,
INIT_3A => PM_Inst_RAM_Word7_INIT_3A,
INIT_3B => PM_Inst_RAM_Word7_INIT_3B,
INIT_3C => PM_Inst_RAM_Word7_INIT_3C,
INIT_3D => PM_Inst_RAM_Word7_INIT_3D,
INIT_3E => PM_Inst_RAM_Word7_INIT_3E,
INIT_3F => PM_Inst_RAM_Word7_INIT_3F
)
port map(
DO => RAMBlDOut(8)(15 downto 0),
ADDR => address(9 downto 0),
DI => din(15 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(8)
);
--end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 10)));
end RTL;

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XPM is
-- Stop Xilinx Tools optimizing the memories because the contents are identical
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of address : signal is "no";
type ram_type is array (SIZE - 1 downto 0) of std_logic_vector (WIDTH - 1 downto 0);
signal RAM : ram_type;
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;

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src/AVR8/Memory/XPM_T65.vhd Normal file
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src/AVR8/Memory/XPM_Xilinx.vhd Normal file
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
library unisim;
use unisim.vcomponents.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XPM is
-- number of bits in the RAMB16_S18
constant ramb16_size : integer := 16384;
-- determine shape of memory
constant block_size : integer := ramb16_size / WIDTH;
constant block_bits : integer := f_log2(block_size);
constant num_blocks : integer := (SIZE + block_size - 1) / block_size;
type RAMBlDOut_Type is array(0 to num_blocks - 1) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
begin
RAM_Inst:for i in 0 to num_blocks - 1 generate
Ram : RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map(
DO => RAMBlDOut(i),
ADDR => address(block_bits - 1 downto 0),
DI => din,
DIP => "11",
EN => ce,
SSR => '0',
CLK => cp2,
WE => '0'
);
end generate;
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto block_bits)));
end RTL;

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src/AVR8/Memory/prog_mem_init.vhd
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@ -1,558 +0,0 @@
-- VHDL initialization records.
--
-- Release 11.1i - Data2MEM L.33, build 1.5.8 Jul 23, 2008
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--
-- Command: C:\Users\ZBAND0~1\AppData\Local\Temp\build5746311222132730322.tmp\data2mem.exe -bm bitstreams/custom_bd.bmm -bd out.mem -o h E:\Papilio\Cores\GadgetFactory_Arduino_Timer_Counter\AVR8_SoftCore_TimerCounter_SPI\sources\Memory\prog_mem_init.vhd
--
-- Created on 11/24/12 01:13 pm, from:
--
-- Map file - bitstreams\custom_bd.bmm
-- Data file(s) - out.mem
--
-- Address space 'avrmap.rom_code' [0x00000000:0x00003FFF], 16384 bytes in size.
--
-- Bus width = 16 bits, bit lane width = 16 bits, number of bus blocks = 8.
library ieee;
use ieee.std_logic_1164;
package prog_mem_init_pkg is
-- BRAM 0 in address space [0x00000000:0x000007FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word0 LOC = RAMB16_X0Y4;
constant PM_Inst_RAM_Word0_INIT_00 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C0098940C";
constant PM_Inst_RAM_Word0_INIT_01 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C00C7940C";
constant PM_Inst_RAM_Word0_INIT_02 : bit_vector(0 to 255) := x"00C7940C00C7940C00C7940C00C7940C00C7940C1644940C00C7940C1539940C";
constant PM_Inst_RAM_Word0_INIT_03 : bit_vector(0 to 255) := x"000000280022003100340037003A0000005C222A2C3B5D5B2F3F3D2B5E3E3C7C";
constant PM_Inst_RAM_Word0_INIT_04 : bit_vector(0 to 255) := x"010101010101002000210030003300360039000000270023003200350038003B";
constant PM_Inst_RAM_Word0_INIT_05 : bit_vector(0 to 255) := x"0505050505050404040404040404030303030303030302020202020202020101";
constant PM_Inst_RAM_Word0_INIT_06 : bit_vector(0 to 255) := x"2010080402018040201008040201804020100804020106060606060606060505";
constant PM_Inst_RAM_Word0_INIT_07 : bit_vector(0 to 255) := x"0000000000008040201008040201804020100804020180402010080402018040";
constant PM_Inst_RAM_Word0_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000005000001000000000000";
constant PM_Inst_RAM_Word0_INIT_09 : bit_vector(0 to 255) := x"E6A0E011BFCDBFDEE0DFEFCFBE1F241116DD1193000000000000000000000000";
constant PM_Inst_RAM_Word0_INIT_0A : bit_vector(0 to 255) := x"E014BE1BF7C907B131A2F3C89631920D95D8C004BF0B9503EF0FE3F2E1E2E0B0";
constant PM_Inst_RAM_Word0_INIT_0B : bit_vector(0 to 255) := x"1901940E2FEC2FFD9722C005E0D1E3C0E011F7E107B131AB921DC001E0B1E1A2";
constant PM_Inst_RAM_Word0_INIT_0C : bit_vector(0 to 255) := x"9001918DC0042FB92FA82FF72FE60000940C1907940C170E940EF7C107D132CC";
constant PM_Inst_RAM_Word0_INIT_0D : bit_vector(0 to 255) := x"9508E0808385E186F02030672FF92FE895080B991B88F7C840505041F4211980";
constant PM_Inst_RAM_Word0_INIT_0E : bit_vector(0 to 255) := x"E090C002FD22B14DB98D7F8CB18D9A70C0019870F4113066C002FD60E0302F26";
constant PM_Inst_RAM_Word0_INIT_0F : bit_vector(0 to 255) := x"93DF93CF931F930F92FF9508E081B98D2B892B8470812F8295279536E092C001";
constant PM_Inst_RAM_Word0_INIT_10 : bit_vector(0 to 255) := x"C008E081F4113F8FB18FCFFE9B77B8FF94FA24FF2FD72FC61581940E2F172F06";
constant PM_Inst_RAM_Word0_INIT_11 : bit_vector(0 to 255) := x"2FF92FE8950890FF910F911F91CF91DFE080F388077117600B7D1B6C1581940E";
constant PM_Inst_RAM_Word0_INIT_12 : bit_vector(0 to 255) := x"2F84B96F2FB92FA8950815FC940EE06181842FF92FE8950815FC940EE0608184";
constant PM_Inst_RAM_Word0_INIT_13 : bit_vector(0 to 255) := x"96324F3F5F2EB98F8181CFFE9B77B98F8180CFFE9B77E030E0202FF92FE82F95";
constant PM_Inst_RAM_Word0_INIT_14 : bit_vector(0 to 255) := x"B98FEF8FCFFE9B77B98FEF8FCFFE9B77B98FEF8FCFFE9B77F78907383020E082";
constant PM_Inst_RAM_Word0_INIT_15 : bit_vector(0 to 255) := x"2F8A9715938C9615E1819508E081F4113085718F971A938C961AB18FCFFE9B77";
constant PM_Inst_RAM_Word0_INIT_16 : bit_vector(0 to 255) := x"2F172F061581940E2FD92FC893DF93CF931F930F92FF9508E0800125940E2F9B";
constant PM_Inst_RAM_Word0_INIT_17 : bit_vector(0 to 255) := x"B18FCFFE9B77B8FFC00CE08FF0104071526D0B711B601581940EC00994FA24FF";
constant PM_Inst_RAM_Word0_INIT_18 : bit_vector(0 to 255) := x"91CF91DFE0800125940E2F9D2F8C838DE08DC007E081F4113F8EF3813F8F878A";
constant PM_Inst_RAM_Word0_INIT_19 : bit_vector(0 to 255) := x"EF4F8538812FB98FEF8FF0D12388818E2FD92FC893DF93CF950890FF910F911F";
constant PM_Inst_RAM_Word0_INIT_1A : bit_vector(0 to 255) := x"CFFE9B77832F8738F3A84092508197012F932F824F3F5F2FB94FCFFE9B77C003";
constant PM_Inst_RAM_Word0_INIT_1B : bit_vector(0 to 255) := x"2FC893DF93CF931F930F92FF92EF92DF950891CF91DF821E0125940E2F9D2F8C";
constant PM_Inst_RAM_Word0_INIT_1C : bit_vector(0 to 255) := x"E071E26C2F9D2F8C011E940E2F9D2F8C0194940E2F152F042EF32EE22ED62FD9";
constant PM_Inst_RAM_Word0_INIT_1D : bit_vector(0 to 255) := x"95B6C0042E022D8E2D9F2FA02FB1E030E128CFFE9B77B98F64802D8D00FB940E";
constant PM_Inst_RAM_Word0_INIT_1E : bit_vector(0 to 255) := x"F41120DDF75907383F28EF8F40305028CFFE9B77B98FF7D2940A9587959795A7";
constant PM_Inst_RAM_Word0_INIT_1F : bit_vector(0 to 255) := x"CFFE9B77B92FEF2FE090CFFE9B77B98FEF8FC001E887F41116D8E088C006E985";
constant PM_Inst_RAM_Word0_INIT_20 : bit_vector(0 to 255) := x"92DF92CF950890DF90EF90FF910F911F91CF91DF878AF7C15091C002FF87B18F";
constant PM_Inst_RAM_Word0_INIT_21 : bit_vector(0 to 255) := x"055115412ED32EC22F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF";
constant PM_Inst_RAM_Word0_INIT_22 : bit_vector(0 to 255) := x"2F8CF7D1952A1F111F001CFF0CEEE029F0393083858BC03DE182F41105710561";
constant PM_Inst_RAM_Word0_INIT_23 : bit_vector(0 to 255) := x"2D4CEF6E2F9D2F8CC026E084F011238801B8940E2D2E2D3F2F402F51E1682F9D";
constant PM_Inst_RAM_Word0_INIT_24 : bit_vector(0 to 255) := x"2F8CC013E185F411238800FB940EE072E5682F9D2F8CF0F12388012C940E2D5D";
constant PM_Inst_RAM_Word0_INIT_25 : bit_vector(0 to 255) := x"2388B18FCFFE9B77B98FEF8FF439238801B8940EE050E040E030E020E06D2F9D";
constant PM_Inst_RAM_Word0_INIT_26 : bit_vector(0 to 255) := x"90CF90DF90EF90FF910F911F91CF91DFE0800125940E2F9D2F8C838DE184F081";
constant PM_Inst_RAM_Word0_INIT_27 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928FCFF1E0810125940E2F9D2F8C9508";
constant PM_Inst_RAM_Word0_INIT_28 : bit_vector(0 to 255) := x"2F80C081F409051115012E932E822ED72EC62EB52EA42FD92FC893DF93CF931F";
constant PM_Inst_RAM_Word0_INIT_29 : bit_vector(0 to 255) := x"0759174881BB81AA81998188F0712388818EC073F008409250811F930F822F91";
constant PM_Inst_RAM_Word0_INIT_2A : bit_vector(0 to 255) := x"E069F0393083858B82DB82CA82B982A8F538069916888598818FF429077B076A";
constant PM_Inst_RAM_Word0_INIT_2B : bit_vector(0 to 255) := x"238801B8940E2D2A2D3B2D4C2D5DE1612F9D2F8CF7D1956A1CDD1CCC1CBB0CAA";
constant PM_Inst_RAM_Word0_INIT_2C : bit_vector(0 to 255) := x"EF8F838EE081821F8618C03FF40923880165940E2F9D2F8CC046838DE083F019";
constant PM_Inst_RAM_Word0_INIT_2D : bit_vector(0 to 255) := x"2FB12FA0838F8798F3C8059915889601B92FCFFE9B77C004EF2F8598818FB98F";
constant PM_Inst_RAM_Word0_INIT_2E : bit_vector(0 to 255) := x"4F3F5F2FB99F83801FF30FE22DFF2DEEB18FCFFE9B77C00BEF9FE030E0209711";
constant PM_Inst_RAM_Word0_INIT_2F : bit_vector(0 to 255) := x"8589832F87381F310F208538812F938C1DBF0DAEB18FCFFE9B77F390073B172A";
constant PM_Inst_RAM_Word0_INIT_30 : bit_vector(0 to 255) := x"C001E0800125940E2F9D2F8CC0060194940E2F9D2F8CF05840325020F0192388";
constant PM_Inst_RAM_Word0_INIT_31 : bit_vector(0 to 255) := x"92FF92EF9508908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE081";
constant PM_Inst_RAM_Word0_INIT_32 : bit_vector(0 to 255) := x"92BF950890EF90FF910F911F0277940EE012E000E030E0202EF32EE2931F930F";
constant PM_Inst_RAM_Word0_INIT_33 : bit_vector(0 to 255) := x"834C821D821E8619861B2EB62FD92FC893DF93CF931F930F92FF92EF92DF92CF";
constant PM_Inst_RAM_Word0_INIT_34 : bit_vector(0 to 255) := x"15D4940EE060E08C0125940E2F9D2F8C15D4940EE061818C2ED72EC61581940E";
constant PM_Inst_RAM_Word0_INIT_35 : bit_vector(0 to 255) := x"E0809870B98DE58315D4940EE061E08A15D4940EE061E08D15D4940EE061E08B";
constant PM_Inst_RAM_Word0_INIT_36 : bit_vector(0 to 255) := x"097D196C1581940EC009011E940E2F9D2F8CF7D1308A5F8FCFFE9B77B99FEF9F";
constant PM_Inst_RAM_Word0_INIT_37 : bit_vector(0 to 255) := x"878A2F1801B8940EE050E040E030E020E0602F9D2F8CC065E081F01040775D61";
constant PM_Inst_RAM_Word0_INIT_38 : bit_vector(0 to 255) := x"E080C010871BC002FF8201B8940EE050E040E031EA2AE0682F9D2F8CF7513081";
constant PM_Inst_RAM_Word0_INIT_39 : bit_vector(0 to 255) := x"858B878BE082C03DE082F0113A9A879AF7C930845F8FB19FCFFE9B77B92FEF2F";
constant PM_Inst_RAM_Word0_INIT_3A : bit_vector(0 to 255) := x"196C1581940EC0092F17E4702D012CF12CE1C00F2711270024FF24EEF0293082";
constant PM_Inst_RAM_Word0_INIT_3B : bit_vector(0 to 255) := x"2F8C01B8940EE050E040E030E020E3672F9D2F8CC024E088F01040775D61097D";
constant PM_Inst_RAM_Word0_INIT_3C : bit_vector(0 to 255) := x"2F9D2F8CF5313082858BF7112388878A01B8940E2D2E2D3F2F402F51E2692F9D";
constant PM_Inst_RAM_Word0_INIT_3D : bit_vector(0 to 255) := x"E0800125940E2F9D2F8C838DE086F041238801B8940EE050E040E030E020E36A";
constant PM_Inst_RAM_Word0_INIT_3E : bit_vector(0 to 255) := x"CFFE9B77B99FEF9FE080878BE083F4113C807C80B18FCFFE9B77B98FEF8FC01C";
constant PM_Inst_RAM_Word0_INIT_3F : bit_vector(0 to 255) := x"911F91CF91DF00D8940E2D6B2F9D2F8C0125940E2F9D2F8CF7C930835F8FB12F";
-- BRAM 0 in address space [0x00000800:0x00000FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word1 LOC = RAMB16_X0Y8;
constant PM_Inst_RAM_Word1_INIT_00 : bit_vector(0 to 255) := x"E220E090E0802FB72FA62FD92FC893DF93CF950890BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word1_INIT_01 : bit_vector(0 to 255) := x"E090E680F019322EC024E040E057F7B90591308B960183201FF90FE82FFB2FEA";
constant PM_Inst_RAM_Word1_INIT_02 : bit_vector(0 to 255) := x"1754F7B923332D3095C896012FF92FE8F1091732C01AE048E05AF131305AC007";
constant PM_Inst_RAM_Word1_INIT_03 : bit_vector(0 to 255) := x"5F4F83201DF10FE42FFB2FEA5220F408318A56812F82F4A0372FF0B03221F0C0";
constant PM_Inst_RAM_Word1_INIT_04 : bit_vector(0 to 255) := x"927F926F950891CF91DF2F89E090C001E091F0193280918CE090F6C923229129";
constant PM_Inst_RAM_Word1_INIT_05 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F";
constant PM_Inst_RAM_Word1_INIT_06 : bit_vector(0 to 255) := x"C07BF40807B707A60795178489BD89AC899B898AC085F4092322812C2F172F06";
constant PM_Inst_RAM_Word1_INIT_07 : bit_vector(0 to 255) := x"8529C06A861C861B861A86198618821F821E821DF4490511050104F114E1C08A";
constant PM_Inst_RAM_Word1_INIT_08 : bit_vector(0 to 255) := x"2E952E842E732E6240504040403050219609E09085858DFB8DEA855C854B853A";
constant PM_Inst_RAM_Word1_INIT_09 : bit_vector(0 to 255) := x"090108F108E194084F5F4F4F4F3F5F2FF7D2940A9467947794879496C0042E08";
constant PM_Inst_RAM_Word1_INIT_0A : bit_vector(0 to 255) := x"1D011CF11CE19408F7D2958A94A794B794C794D6C0042ED12EC02CBF2CAE0911";
constant PM_Inst_RAM_Word1_INIT_0B : bit_vector(0 to 255) := x"838D8DB98DA8899F898EF4490551054105311521F02804D904C804B714A61D11";
constant PM_Inst_RAM_Word1_INIT_0C : bit_vector(0 to 255) := x"2D288D9B8D8A8578816F815E814DC01208D908C808B718A6C01787B883AF839E";
constant PM_Inst_RAM_Word1_INIT_0D : bit_vector(0 to 255) := x"1E9D0E8C2C912E88E085C010F431238808D108C108B108A194080F04940E2D39";
constant PM_Inst_RAM_Word1_INIT_0E : bit_vector(0 to 255) := x"910F911F91CF91DFE080C001E081871C870B86FA86E9F72104D104C104B114A1";
constant PM_Inst_RAM_Word1_INIT_0F : bit_vector(0 to 255) := x"93CFCFE6CF73F00930229508906F907F908F909F90AF90BF90CF90DF90EF90FF";
constant PM_Inst_RAM_Word1_INIT_10 : bit_vector(0 to 255) := x"8989C00AE030E020F41923880CC5940E8998858F857E856D2F462FD92FC893DF";
constant PM_Inst_RAM_Word1_INIT_11 : bit_vector(0 to 255) := x"931F930F950891CF91DF2F932F824F3E5E2CF7E1959A1F330F22E095E0302F28";
constant PM_Inst_RAM_Word1_INIT_12 : bit_vector(0 to 255) := x"E0612F912F80C03DFF878183C043F409238881842FF92FE82F192F0893DF93CF";
constant PM_Inst_RAM_Word1_INIT_13 : bit_vector(0 to 255) := x"8F8C89B589A489938982F440308281842FF12FE0F1B997002FD92FC804FF940E";
constant PM_Inst_RAM_Word1_INIT_14 : bit_vector(0 to 255) := x"27AA2F8A2F9B8DB18DA0899789868F8A8F9B899789862FF12FE08FBF8FAE8F9D";
constant PM_Inst_RAM_Word1_INIT_15 : bit_vector(0 to 255) := x"96482F9D2F8C4F7F5E6A2F7D2F6CF0619730011391F0011291E08B8C8B9D27BB";
constant PM_Inst_RAM_Word1_INIT_16 : bit_vector(0 to 255) := x"91CF91DFE080C0010C64940E8383778F81832FF12FE08B8A8B9B8D998D889509";
constant PM_Inst_RAM_Word1_INIT_17 : bit_vector(0 to 255) := x"950891CF91DFE081821CF0112388051E940E2FD92FC893DF93CF9508910F911F";
constant PM_Inst_RAM_Word1_INIT_18 : bit_vector(0 to 255) := x"D000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F";
constant PM_Inst_RAM_Word1_INIT_19 : bit_vector(0 to 255) := x"C0A1F00930819714918C96142FB92FA82ED72EC62EB52EA42EF92EE8B7DEB7CD";
constant PM_Inst_RAM_Word1_INIT_1A : bit_vector(0 to 255) := x"8483847284612DFF2DEEC097E081F41105B105A19700C0B0C09DFF81918C9613";
constant PM_Inst_RAM_Word1_INIT_1B : bit_vector(0 to 255) := x"918D965A2DBF2DAEC085F4092388044E940E2D4A2D5B2D6C2D7D2D9F2D8E8494";
constant PM_Inst_RAM_Word1_INIT_1C : bit_vector(0 to 255) := x"23880F82940E9759917C916D915D914D9656F49104D104C104B114A1975B919C";
constant PM_Inst_RAM_Word1_INIT_1D : bit_vector(0 to 255) := x"917C916D915D914D96152DBF2DAEC0428E118E108A178A162DFF2DEEC06FF409";
constant PM_Inst_RAM_Word1_INIT_1E : bit_vector(0 to 255) := x"975B91FC91ED965A2DBF2DAEC057F40923880F04940E4F3F5F2F2F3D2F2C9718";
constant PM_Inst_RAM_Word1_INIT_1F : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987817C816B815A8149";
constant PM_Inst_RAM_Word1_INIT_20 : bit_vector(0 to 255) := x"8167815681452DFF2DEEF1B123880F82940E2F9F2F8EF4B0077B076A07591748";
constant PM_Inst_RAM_Word1_INIT_21 : bit_vector(0 to 255) := x"92BD92AD96522DBF2DAEF13123880E5B940EE03FEF2FEF1FEF0F8D938D828570";
constant PM_Inst_RAM_Word1_INIT_22 : bit_vector(0 to 255) := x"2D7DF0912388051E940E2D9F2D8E938C961368809713918C9613975592DC92CD";
constant PM_Inst_RAM_Word1_INIT_23 : bit_vector(0 to 255) := x"044E940E2D9F2D8E2D462D572D682D79F420049D048C047B146A2D4A2D5B2D6C";
constant PM_Inst_RAM_Word1_INIT_24 : bit_vector(0 to 255) := x"90AF90BF90CF90DF90EF90FF910F911F91DF91CF900F900F900F900FE080C001";
constant PM_Inst_RAM_Word1_INIT_25 : bit_vector(0 to 255) := x"F00807B707A60795178489B589A4899389822DFF2DEE9508906F907F908F909F";
constant PM_Inst_RAM_Word1_INIT_26 : bit_vector(0 to 255) := x"92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922FCFDFCF44";
constant PM_Inst_RAM_Word1_INIT_27 : bit_vector(0 to 255) := x"C0EDC0D7FF80818BC0DAF4092388818C2E552E442FD92FC893DF93CF931F930F";
constant PM_Inst_RAM_Word1_INIT_28 : bit_vector(0 to 255) := x"C0BF2C752C641E3D0E2C2C312E27E0752E932E822F372F26085F184E2C5B2C4A";
constant PM_Inst_RAM_Word1_INIT_29 : bit_vector(0 to 255) := x"E0992F152F042EF32EE2818C22B322A22EB6E0612EA6EF6F855C854B853A8529";
constant PM_Inst_RAM_Word1_INIT_2A : bit_vector(0 to 255) := x"1D5F0D4E8D758D648D538D42F44930828DFB8DEAF7D1959A94E794F795079516";
constant PM_Inst_RAM_Word1_INIT_2B : bit_vector(0 to 255) := x"F4490551054105311521F4D920DDF4E904B114A120DE94DA80D4C0411F711F60";
constant PM_Inst_RAM_Word1_INIT_2C : bit_vector(0 to 255) := x"2D222F9F2F8E8578816F815E814DC00D87B883AF839E838D8DB98DA8899F898E";
constant PM_Inst_RAM_Word1_INIT_2D : bit_vector(0 to 255) := x"40704060405050428578816F815E814D8DFB8DEAC080F40923880F04940E2D33";
constant PM_Inst_RAM_Word1_INIT_2E : bit_vector(0 to 255) := x"1F7B1F6A1F590F4889B189A085978586F7D2940A1F771F661F550F44C0048405";
constant PM_Inst_RAM_Word1_INIT_2F : bit_vector(0 to 255) := x"818B2ED92EC8F410059715862CD72CC6099B198AE092E0801D711D611D510D4D";
constant PM_Inst_RAM_Word1_INIT_30 : bit_vector(0 to 255) := x"00FC91B000FB91A000FA919000F99180C080F00906D8E08216C8E080C006FD86";
constant PM_Inst_RAM_Word1_INIT_31 : bit_vector(0 to 255) := x"2CF92CE82D1D2D0C2D3B2D2A0315919003149180C072F409077B076A07591748";
constant PM_Inst_RAM_Word1_INIT_32 : bit_vector(0 to 255) := x"2DA81D5D0D4C2F532F424F3E5E2C2D3B2D2AC0161C9D0C8CF19123880277940E";
constant PM_Inst_RAM_Word1_INIT_33 : bit_vector(0 to 255) := x"E0402D3D2D2C1E9F0E8E0BF31BE2F7D907F517E4938D9181C0022FF32FE22DB9";
constant PM_Inst_RAM_Word1_INIT_34 : bit_vector(0 to 255) := x"1461087D186C87BC87AB879A87891FB51FA41F930F8285BC85AB859A8589E050";
constant PM_Inst_RAM_Word1_INIT_35 : bit_vector(0 to 255) := x"90EF90FF910F911F91CF91DF2F952F84EF5FEF4FC0022D552D44CF3DF0090471";
constant PM_Inst_RAM_Word1_INIT_36 : bit_vector(0 to 255) := x"88CC88BB88AA9508902F903F904F905F906F907F908F909F90AF90BF90CF90DF";
constant PM_Inst_RAM_Word1_INIT_37 : bit_vector(0 to 255) := x"0BA0099F198E2D8A2D9B2DAC2DBDE050E0402F352F24851C850B84FA84E988DD";
constant PM_Inst_RAM_Word1_INIT_38 : bit_vector(0 to 255) := x"23880CC5940EE0402F642F752F862F97CEFCCEF9F40807B507A4079317820BB1";
constant PM_Inst_RAM_Word1_INIT_39 : bit_vector(0 to 255) := x"2ED92EC8B7DEB7CD920F93CF93DF931F930F92FF92EF92DF92CFCFC3CF95F009";
constant PM_Inst_RAM_Word1_INIT_3A : bit_vector(0 to 255) := x"E0414F7F5F6F2F7D2F6C2D9D2D8C8514850384F284E1F080308281842FF92FE8";
constant PM_Inst_RAM_Word1_INIT_3B : bit_vector(0 to 255) := x"90EF90FF910F911F91DF91CF900F2F932F82E030E020F07197010662940EE050";
constant PM_Inst_RAM_Word1_INIT_3C : bit_vector(0 to 255) := x"87B487A3879287811DB11DA1964F85B485A3859285812DFD2DEC950890CF90DF";
constant PM_Inst_RAM_Word1_INIT_3D : bit_vector(0 to 255) := x"F7E195EA1F330F22E0E5E0302F28708F2D8EF7D195FA94E794F795079516E0F5";
constant PM_Inst_RAM_Word1_INIT_3E : bit_vector(0 to 255) := x"2FE6C045F0092388818C2F172F062FD92FC893DF93CF931F930FCFD44F3E5E2C";
constant PM_Inst_RAM_Word1_INIT_3F : bit_vector(0 to 255) := x"0F88E045E0B0E0A08D918D808E198E188A1F8A1E838CE082F4B1318089872FF7";
-- BRAM 0 in address space [0x00001000:0x000017FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word2 LOC = RAMB16_X0Y1;
constant PM_Inst_RAM_Word2_INIT_00 : bit_vector(0 to 255) := x"2FF72FE6838CE083F5413280C0188BBD8BAC8B9B8B8AF7D1954A1FBB1FAA1F99";
constant PM_Inst_RAM_Word2_INIT_01 : bit_vector(0 to 255) := x"0FE8940E2F912F804F3F5E2E2F3D2F2C8F798F688B5F8B4E8D758D648D538D42";
constant PM_Inst_RAM_Word2_INIT_02 : bit_vector(0 to 255) := x"861E861D861C861B861A86198618821F821E821D838BE0818F0A8F1BF0912388";
constant PM_Inst_RAM_Word2_INIT_03 : bit_vector(0 to 255) := x"2F142FD92FC893DF93CF931F9508910F911F91CF91DFE080C0018A198A18861F";
constant PM_Inst_RAM_Word2_INIT_04 : bit_vector(0 to 255) := x"C057F00974822F84F021718185834FFE5EECF7E1957A1FFF0FEEE075E0F02FE6";
constant PM_Inst_RAM_Word2_INIT_05 : bit_vector(0 to 255) := x"E0A0899589848BB887AF879E878D00FC91B000FB91A000FA919000F991808B69";
constant PM_Inst_RAM_Word2_INIT_06 : bit_vector(0 to 255) := x"8F688B5F8B4E2B7B2B6A2B592B48E0B0E0A08D938D82274427552F792F68E0B0";
constant PM_Inst_RAM_Word2_INIT_07 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A8DB78DA68D958D84F451970070907188E09085838F79";
constant PM_Inst_RAM_Word2_INIT_08 : bit_vector(0 to 255) := x"2F81838CE084F0D123880FE8940E8D9B8D8A4F3F5E2E2F3D2F2CF5219740C00D";
constant PM_Inst_RAM_Word2_INIT_09 : bit_vector(0 to 255) := x"2F9D2F8CC00AE081C002FD16861C861B861A86198618821F821E821D838B708F";
constant PM_Inst_RAM_Word2_INIT_0A : bit_vector(0 to 255) := x"2FD92FC893DF93CF9508911F91CF91DFE080C0010580940EE070E060E050E040";
constant PM_Inst_RAM_Word2_INIT_0B : bit_vector(0 to 255) := x"899F898EF0A123881061940EE070E060E050E0418D9B8D8A4F3F5F2B2F392F28";
constant PM_Inst_RAM_Word2_INIT_0C : bit_vector(0 to 255) := x"6880818B8FB98FA88B9F8B8E85B881AF819E818DF45905B105A197008DB98DA8";
constant PM_Inst_RAM_Word2_INIT_0D : bit_vector(0 to 255) := x"92DF92CF92BF92AF929F928F927F925F924F923F922F950891CF91DFE081838B";
constant PM_Inst_RAM_Word2_INIT_0E : bit_vector(0 to 255) := x"835E2F072F162ED92EC8B7DEB7CDD000D000D00093CF93DF931F930F92FF92EF";
constant PM_Inst_RAM_Word2_INIT_0F : bit_vector(0 to 255) := x"2DFD2DECC1B1C191FF81918C9613C195F00930819714918C96142FB92FA8834D";
constant PM_Inst_RAM_Word2_INIT_10 : bit_vector(0 to 255) := x"940E2D9D2D8CF03907B707A60795178485B485A3859285818975896489538942";
constant PM_Inst_RAM_Word2_INIT_11 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DACC132803E802D2E532E422F302F21C17AF4092388044E";
constant PM_Inst_RAM_Word2_INIT_12 : bit_vector(0 to 255) := x"EF7F2278947A8074F7D1951A9587959795A795B6E0192F822F932FA42FB5975B";
constant PM_Inst_RAM_Word2_INIT_13 : bit_vector(0 to 255) := x"914D96152DBD2DACC053F00904911481C057F0092077229322822E97E0712E87";
constant PM_Inst_RAM_Word2_INIT_14 : bit_vector(0 to 255) := x"97002DA091BC900D919D918D9656F48905710561055115419718917C916D915D";
constant PM_Inst_RAM_Word2_INIT_15 : bit_vector(0 to 255) := x"4F3F5F2F2F3D2F2C2F9F2F8EC03587B083A7839683852DFD2DECF17905B105A1";
constant PM_Inst_RAM_Word2_INIT_16 : bit_vector(0 to 255) := x"91FC91ED965A2DBD2DAC815C814B813A8129C12EE050E040F41923880F04940E";
constant PM_Inst_RAM_Word2_INIT_17 : bit_vector(0 to 255) := x"074A07391728E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987975B";
constant PM_Inst_RAM_Word2_INIT_18 : bit_vector(0 to 255) := x"E08087508347833683252DFD2DECC105F439238808AC940E2D9D2D8CF038075B";
constant PM_Inst_RAM_Word2_INIT_19 : bit_vector(0 to 255) := x"975B91FC91ED965A2DBD2DAC2EB92EA8F410059315822CB32CA209991988E092";
constant PM_Inst_RAM_Word2_INIT_1A : bit_vector(0 to 255) := x"C00484051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E9718911C910D90FD90ED9615";
constant PM_Inst_RAM_Word2_INIT_1B : bit_vector(0 to 255) := x"1CF10CE71F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEE";
constant PM_Inst_RAM_Word2_INIT_1C : bit_vector(0 to 255) := x"158E00FC91B000FB91A000FA919000F99180F56906B9E09216A9E0901D111D01";
constant PM_Inst_RAM_Word2_INIT_1D : bit_vector(0 to 255) := x"00FC93B000FB93A000FA939000F99380EFBFEFAFEF9FEF8FF46107B107A0059F";
constant PM_Inst_RAM_Word2_INIT_1E : bit_vector(0 to 255) := x"E0A0C09FF4092388020E940E2D352D242D4E2D5F2F602F710315919003149180";
constant PM_Inst_RAM_Word2_INIT_1F : bit_vector(0 to 255) := x"89A48993898285548543853285212DFD2DECF51104911481C0451E5B0E4AE0B2";
constant PM_Inst_RAM_Word2_INIT_20 : bit_vector(0 to 255) := x"930000FA92F000F992E0C083F40923880C64940EF098075B074A0739172889B5";
constant PM_Inst_RAM_Word2_INIT_21 : bit_vector(0 to 255) := x"0CC5940EE0412D6E2D7F2F802F91C00A0316938060810316918000FC931000FB";
constant PM_Inst_RAM_Word2_INIT_22 : bit_vector(0 to 255) := x"C0022FF32FE22DB52DA41D5B0D4A2F532F424F3E5E2C2D392D28C06BF4092388";
constant PM_Inst_RAM_Word2_INIT_23 : bit_vector(0 to 255) := x"2DECE050E0402D3B2D2A083B182A1E5F0E4E0BF31BE2F7D907F517E49381918D";
constant PM_Inst_RAM_Word2_INIT_24 : bit_vector(0 to 255) := x"96192DBD2DAC87B487A3879287811FB51FA41F930F8285B485A3859285812DFD";
constant PM_Inst_RAM_Word2_INIT_25 : bit_vector(0 to 255) := x"17822DA091BC900D919D918D9652CEC2F00904311421971C915C914D913D912D";
constant PM_Inst_RAM_Word2_INIT_26 : bit_vector(0 to 255) := x"01129180C0128383688081838B558B448B338B222DFD2DECF45007B507A40793";
constant PM_Inst_RAM_Word2_INIT_27 : bit_vector(0 to 255) := x"938C961368809713918C96132DBD2DACF0412B89819E818DF0612B8901139190";
constant PM_Inst_RAM_Word2_INIT_28 : bit_vector(0 to 255) := x"2DACE081C007815E814DF0192388051E940E2D9D2D8CC006FF8381832DFD2DEC";
constant PM_Inst_RAM_Word2_INIT_29 : bit_vector(0 to 255) := x"911F91DF91CFBFCDBE0FBFDE94F8B60F96262F952F84EF5FEF4F938C96122DBD";
constant PM_Inst_RAM_Word2_INIT_2A : bit_vector(0 to 255) := x"FD829508902F903F904F905F907F908F909F90AF90BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word2_INIT_2B : bit_vector(0 to 255) := x"08D5940E2F5B2F4A0BBF1BAE9711F7E92000900D2FBF2FAE2FF72FE6CE62CE4D";
constant PM_Inst_RAM_Word2_INIT_2C : bit_vector(0 to 255) := x"900F08D5940EE050E0414F7F5F6F2F7D2F6C8369B7DEB7CD920F93CF93DF9508";
constant PM_Inst_RAM_Word2_INIT_2D : bit_vector(0 to 255) := x"F409238808AC940E2FD92FC893DF93CF931F930F92FF92EF92DF950891DF91CF";
constant PM_Inst_RAM_Word2_INIT_2E : bit_vector(0 to 255) := x"84051F1B1F0A1EF90EE8EFBFEFAFEF9FEF8E8518810F80FE80ED8DFB8DEAC050";
constant PM_Inst_RAM_Word2_INIT_2F : bit_vector(0 to 255) := x"80D41F1B1F0A1EF90EE889B189A085978586F7D2940A1F111F001CFF0CEEC004";
constant PM_Inst_RAM_Word2_INIT_30 : bit_vector(0 to 255) := x"0C9F940E1D911D811D710D6D2D6E2D7F2F802F91C00D0911090108F108E19408";
constant PM_Inst_RAM_Word2_INIT_31 : bit_vector(0 to 255) := x"1F441F330F22C0048405E050E040E032E0208DFB8DEAF78920DD94DAF0F92388";
constant PM_Inst_RAM_Word2_INIT_32 : bit_vector(0 to 255) := x"E0818BBD8BAC8B9B8B8A1FB51FA41F930F8289BD89AC899B898AF7D2940A1F55";
constant PM_Inst_RAM_Word2_INIT_33 : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F950890DF90EF90FF910F911F91CF91DFE080C001";
constant PM_Inst_RAM_Word2_INIT_34 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F972BB7DEB7CD93CF93DF931F930F92FF92EF92DF92CF";
constant PM_Inst_RAM_Word2_INIT_35 : bit_vector(0 to 255) := x"2F1D2F0C2F952F84C0F2F0092388918C96142FB92FA82E822ED72EC62EB92EA8";
constant PM_Inst_RAM_Word2_INIT_36 : bit_vector(0 to 255) := x"965B2DBB2DAA8D938D822DFD2DECC0E5F40923880407940E2F712F604F1F5F0F";
constant PM_Inst_RAM_Word2_INIT_37 : bit_vector(0 to 255) := x"2499971C921C921D921D921D96192DBD2DAC8610821782168215975A938E939C";
constant PM_Inst_RAM_Word2_INIT_38 : bit_vector(0 to 255) := x"9516E085C0C0F40997002FF92FE80793940E2D9D2D8CC0492E792E602F912F80";
constant PM_Inst_RAM_Word2_INIT_39 : bit_vector(0 to 255) := x"2DBB2DAAF4992099F4D93E85F01123888180701F2D1EF7D1958A94E794F79507";
constant PM_Inst_RAM_Word2_INIT_3A : bit_vector(0 to 255) := x"935C934D933D932D961D00FC915000FB914000FA913000F991209751931C9651";
constant PM_Inst_RAM_Word2_INIT_3B : bit_vector(0 to 255) := x"2F2800C9940EE050E04B2F7F2F6E2D972D86C02794932499F4C1238881809750";
constant PM_Inst_RAM_Word2_INIT_3C : bit_vector(0 to 255) := x"2DFD2DEC94932499C07E2F612D9B2D8AC086F409338073802D88F4592B232F39";
constant PM_Inst_RAM_Word2_INIT_3D : bit_vector(0 to 255) := x"71822D88CFA7F408071B070A06F916E889B589A4899389828514850384F284E1";
constant PM_Inst_RAM_Word2_INIT_3E : bit_vector(0 to 255) := x"2DACC05FF4A197002F192F0804FF940EE0612D9B2D8AF0512099C06BF0093182";
constant PM_Inst_RAM_Word2_INIT_3F : bit_vector(0 to 255) := x"8A112DFB2DEAC051F40923880AD3940E2D9D2D8CC058F4093082918C96142DBD";
-- BRAM 0 in address space [0x00001800:0x00001FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word3 LOC = RAMB16_X0Y3;
constant PM_Inst_RAM_Word3_INIT_00 : bit_vector(0 to 255) := x"920D9001E08B96312FFD2FEC2FB12FA0F7E9958A921D2FB12FA0E280E011E104";
constant PM_Inst_RAM_Word3_INIT_01 : bit_vector(0 to 255) := x"950996402F912F804F7F5F622F712F60F0499730011391F0011291E0F7E15081";
constant PM_Inst_RAM_Word3_INIT_02 : bit_vector(0 to 255) := x"919C918D96502FB12FA087868797E098E0808B808B912FF12FE0E298E281C00A";
constant PM_Inst_RAM_Word3_INIT_03 : bit_vector(0 to 255) := x"938E939C9657971F919C918D961E9758938E939C96599752938E939C96539751";
constant PM_Inst_RAM_Word3_INIT_04 : bit_vector(0 to 255) := x"962BE080C001083A940E2D4889612DFB2DEA2D9B2D8AF04923880C64940E9756";
constant PM_Inst_RAM_Word3_INIT_05 : bit_vector(0 to 255) := x"909F90AF90BF90CF90DF90EF90FF910F911F91DF91CFBFCDBE0FBFDE94F8B60F";
constant PM_Inst_RAM_Word3_INIT_06 : bit_vector(0 to 255) := x"00FC917000FB916000FA915000F99140F1992388031691809508906F907F908F";
constant PM_Inst_RAM_Word3_INIT_07 : bit_vector(0 to 255) := x"031991600318915003179140F1192388020E940EE031E1240315919003149180";
constant PM_Inst_RAM_Word3_INIT_08 : bit_vector(0 to 255) := x"2388020E940EE031E1240315919003149180F0910571056105511541031A9170";
constant PM_Inst_RAM_Word3_INIT_09 : bit_vector(0 to 255) := x"92EF9508E0809508E08103169210031A9210031992100318921003179210F061";
constant PM_Inst_RAM_Word3_INIT_0A : bit_vector(0 to 255) := x"31E4E0839211E0F1E1E4F0A923880C64940E2F192F082EF72EE6931F930F92FF";
constant PM_Inst_RAM_Word3_INIT_0B : bit_vector(0 to 255) := x"E0810316938060810316918000FC931000FB930000FA92F000F992E0F7D907F8";
constant PM_Inst_RAM_Word3_INIT_0C : bit_vector(0 to 255) := x"91802ED42F192F082EF72EE6931F930F92FF92EF92DF950890EF90FF910F911F";
constant PM_Inst_RAM_Word3_INIT_0D : bit_vector(0 to 255) := x"F0E923880C64940EF0D107B107A0059F158E00FC91B000FB91A000FA919000F9";
constant PM_Inst_RAM_Word3_INIT_0E : bit_vector(0 to 255) := x"00F992E0F0792388031E940EE031E1242D4E2D5F2F602F710315919003149180";
constant PM_Inst_RAM_Word3_INIT_0F : bit_vector(0 to 255) := x"910F911FE080C001E08103169380298D0316918000FC931000FB930000FA92F0";
constant PM_Inst_RAM_Word3_INIT_10 : bit_vector(0 to 255) := x"93DF93CF931F930F92FF92EF92DF92CF92BF92AF929F928F950890DF90EF90FF";
constant PM_Inst_RAM_Word3_INIT_11 : bit_vector(0 to 255) := x"F0083045C04124BB24AA24992488F429234403149360031593702F142ED92EC8";
constant PM_Inst_RAM_Word3_INIT_12 : bit_vector(0 to 255) := x"2FFD2FEC9721E0D02FC1C122F40923880CC5940EE040E090E080E070E060C12C";
constant PM_Inst_RAM_Word3_INIT_13 : bit_vector(0 to 255) := x"2B897090778FE09040F15BEE81804FFE54E24FFE5EECF7E1957A1FFF0FEEE074";
constant PM_Inst_RAM_Word3_INIT_14 : bit_vector(0 to 255) := x"0FCCE064C0FFF40805B105A10591368481B381A2819181804FFE53E6C10BF009";
constant PM_Inst_RAM_Word3_INIT_15 : bit_vector(0 to 255) := x"2D9BC0EEF40904B104A10491148180BB80AA809980884FDD52C6F7E1956A1FDD";
constant PM_Inst_RAM_Word3_INIT_16 : bit_vector(0 to 255) := x"F0094092508001209190011F9180C0E4F40923880CC5940EE0402D682D792D8A";
constant PM_Inst_RAM_Word3_INIT_17 : bit_vector(0 to 255) := x"238801219180C0D0F4092B890123919001229180C0D7F409232201249120C0DC";
constant PM_Inst_RAM_Word3_INIT_18 : bit_vector(0 to 255) := x"87452DFD2DEC5F4FC008E070E06186158384012191808B222DFD2DECC0CBF409";
constant PM_Inst_RAM_Word3_INIT_19 : bit_vector(0 to 255) := x"940A1F330F22C0022E042F372F26E090818485452DFD2DECC0B9F00830485041";
constant PM_Inst_RAM_Word3_INIT_1A : bit_vector(0 to 255) := x"01389120C008E050E040F01905311521012B9130012A9120F74107931782F7E2";
constant PM_Inst_RAM_Word3_INIT_1B : bit_vector(0 to 255) := x"012390F0012290E087508347833683252DFD2DEC013B9150013A914001399130";
constant PM_Inst_RAM_Word3_INIT_1C : bit_vector(0 to 255) := x"8F808F9101269190012591808B168B058AF48AE31D1B1D0A1CF90CE8E010E000";
constant PM_Inst_RAM_Word3_INIT_1D : bit_vector(0 to 255) := x"8F848F738F622DFD2DEC1F911F801D7F0D6E18A2940EE090E080E07001249160";
constant PM_Inst_RAM_Word3_INIT_1E : bit_vector(0 to 255) := x"E040952627332F234F3E5021F7E1955A1F330F22E05501269130012591208F95";
constant PM_Inst_RAM_Word3_INIT_1F : bit_vector(0 to 255) := x"E0A0F019970001289190012791808B518B40873787261F591F481F370F26E050";
constant PM_Inst_RAM_Word3_INIT_20 : bit_vector(0 to 255) := x"0AF31AE22CE82CF92D0A2D1B013791B0013691A00135919001349180C008E0B0";
constant PM_Inst_RAM_Word3_INIT_21 : bit_vector(0 to 255) := x"95479556C00484052DFD2DEC1F5B1F4A1F390F282D2E2D3F2F402F510B150B04";
constant PM_Inst_RAM_Word3_INIT_22 : bit_vector(0 to 255) := x"F410075FE0F0074FE0F0073FE0FF3F258754874387328721F7D2940A95279537";
constant PM_Inst_RAM_Word3_INIT_23 : bit_vector(0 to 255) := x"919001409180C011E0818B872DFD2DECE180F430405040404F3F5F25C006E08C";
constant PM_Inst_RAM_Word3_INIT_24 : bit_vector(0 to 255) := x"91CF91DFE080CFEDE2808FB58FA48F938F822DFD2DEC014391B0014291A00141";
constant PM_Inst_RAM_Word3_INIT_25 : bit_vector(0 to 255) := x"928F927F926F925F924F9508908F909F90AF90BF90CF90DF90EF90FF910F911F";
constant PM_Inst_RAM_Word3_INIT_26 : bit_vector(0 to 255) := x"2EE62ED52EC42FD92FC893DF93CF931F930F92FF92EF92DF92CF92BF92AF929F";
constant PM_Inst_RAM_Word3_INIT_27 : bit_vector(0 to 255) := x"960185BC85AB859A8589C077F40805710561055130422E732E622E512E402EF7";
constant PM_Inst_RAM_Word3_INIT_28 : bit_vector(0 to 255) := x"2799F4293180898F895E894D893C892BC06AF40807B707A6079517841DB11DA1";
constant PM_Inst_RAM_Word3_INIT_29 : bit_vector(0 to 255) := x"2E86F7D1951A9567957795879596E0172D6C2D7D2D8E2D9FC00B2D6D2D7E2D8F";
constant PM_Inst_RAM_Word3_INIT_2A : bit_vector(0 to 255) := x"168800FC91B000FB91A000FA919000F991801EB51EA41E930E822EB92EA82E97";
constant PM_Inst_RAM_Word3_INIT_2B : bit_vector(0 to 255) := x"F4513180898FF1A923880CC5940EE0402D682D792D8A2D9BF04906BB06AA0699";
constant PM_Inst_RAM_Word3_INIT_2C : bit_vector(0 to 255) := x"1FFF0FEE70F077EF2DFD2DECC00E824082514FFE5EEC1FFF0FEE70F02DFD2DEC";
constant PM_Inst_RAM_Word3_INIT_2D : bit_vector(0 to 255) := x"F0803082898A0316938060810316918082738262825182404FFE5EEC1FFF0FEE";
constant PM_Inst_RAM_Word3_INIT_2E : bit_vector(0 to 255) := x"031A92B0031992A003189290031792801EBB1EAA1E990E8885B881AF819E818D";
constant PM_Inst_RAM_Word3_INIT_2F : bit_vector(0 to 255) := x"907F908F909F90AF90BF90CF90DF90EF90FF910F911F91CF91DFE080C001E081";
constant PM_Inst_RAM_Word3_INIT_30 : bit_vector(0 to 255) := x"2EF52EE42FD92FC893DF93CF931F930F92FF92EF92DF92CF9508904F905F906F";
constant PM_Inst_RAM_Word3_INIT_31 : bit_vector(0 to 255) := x"F40807B707A6079517841DB11DA1960185BC85AB859A85892ED32EC22F172F06";
constant PM_Inst_RAM_Word3_INIT_32 : bit_vector(0 to 255) := x"2D7F2F802F91C00B2D6F2F702F812799F4293180898F895E894D893C892BC057";
constant PM_Inst_RAM_Word3_INIT_33 : bit_vector(0 to 255) := x"00FA919000F991801F591F481F370F26F7D195EA9567957795879596E0E72D6E";
constant PM_Inst_RAM_Word3_INIT_34 : bit_vector(0 to 255) := x"0CC5940EE0402F622F732F842F95F049075B074A0739172800FC91B000FB91A0";
constant PM_Inst_RAM_Word3_INIT_35 : bit_vector(0 to 255) := x"E0B0E0A0819181804FFE5EEC1FFF0FEE70F02DFF2DEEF4613180898FF1312388";
constant PM_Inst_RAM_Word3_INIT_36 : bit_vector(0 to 255) := x"70BF81B381A2819181804FFE5EEC1FFF0FEE1FFF0FEE70F077EF2DFF2DEEC00F";
constant PM_Inst_RAM_Word3_INIT_37 : bit_vector(0 to 255) := x"90DF90EF90FF910F911F91CF91DFE080C001E08183B383A2839183802DFD2DEC";
constant PM_Inst_RAM_Word3_INIT_38 : bit_vector(0 to 255) := x"B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF92BF92AF950890CF";
constant PM_Inst_RAM_Word3_INIT_39 : bit_vector(0 to 255) := x"83B383A2839183802DFD2DECE0B0E0A0E090E0822F172F062EF52EE42ED92EC8";
constant PM_Inst_RAM_Word3_INIT_3A : bit_vector(0 to 255) := x"23880F04940E2D3B2D2A2D4E2D5F2F602F712D9D2D8C1CB11CA194082EBD2EAC";
constant PM_Inst_RAM_Word3_INIT_3B : bit_vector(0 to 255) := x"80E9F0C923880E5B940EE030E020E010E0002D4E2D5F2F602F712D9D2D8CF139";
constant PM_Inst_RAM_Word3_INIT_3C : bit_vector(0 to 255) := x"E0A0EF9FEF88C004E0BFEFAFEF9FEF88F029318089872DFD2DEC811C810B80FA";
constant PM_Inst_RAM_Word3_INIT_3D : bit_vector(0 to 255) := x"911F91DF91CF900F900F900F900FE080C001E081F278071B070A06F916E8E0B0";
constant PM_Inst_RAM_Word3_INIT_3E : bit_vector(0 to 255) := x"92BF92AF929F928F927F926F925F924F950890AF90BF90CF90DF90EF90FF910F";
constant PM_Inst_RAM_Word3_INIT_3F : bit_vector(0 to 255) := x"835A83492ED92EC8B7DEB7CDD000D00093CF93DF931F930F92FF92EF92DF92CF";
-- BRAM 0 in address space [0x00002000:0x000027FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word4 LOC = RAMB16_X0Y2;
constant PM_Inst_RAM_Word4_INIT_00 : bit_vector(0 to 255) := x"2E9AE0A22C811C511C4194082E5D2E4C2711270024FF24EE2E732E62837C836B";
constant PM_Inst_RAM_Word4_INIT_01 : bit_vector(0 to 255) := x"2DAA2DBBF17123880F04940E2D352D242D9D2D8C817C816B815A81492CB12CA1";
constant PM_Inst_RAM_Word4_INIT_02 : bit_vector(0 to 255) := x"1F1B1F0A1EF90EE8F7D2940A1FBB1FAA1F990F88C00484052DFD2DEC2D882D99";
constant PM_Inst_RAM_Word4_INIT_03 : bit_vector(0 to 255) := x"E0B0E0A0EF9FEF88C004E0BFEFAFEF9FEF88F02931808987815C814B813A8129";
constant PM_Inst_RAM_Word4_INIT_04 : bit_vector(0 to 255) := x"900F900F900F900FE0818313830282F182E02DF72DE6F268075B074A07391728";
constant PM_Inst_RAM_Word4_INIT_05 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF";
constant PM_Inst_RAM_Word4_INIT_06 : bit_vector(0 to 255) := x"930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F9508";
constant PM_Inst_RAM_Word4_INIT_07 : bit_vector(0 to 255) := x"876C875B874A2E392E28BFCDBE0FBFDE94F8B60F972FB7DEB7CD93CF93DF931F";
constant PM_Inst_RAM_Word4_INIT_08 : bit_vector(0 to 255) := x"2E912E80F0590531052105111501913C912D911D910D2FB32FA2872E873F877D";
constant PM_Inst_RAM_Word4_INIT_09 : bit_vector(0 to 255) := x"861980B380A2809180802FF92FE8C01186191CB11CA11C911C8194082EB32EA2";
constant PM_Inst_RAM_Word4_INIT_0A : bit_vector(0 to 255) := x"900D919D918D96192DB32DA28799E091F41105B105A1970185BD85AC859B858A";
constant PM_Inst_RAM_Word4_INIT_0B : bit_vector(0 to 255) := x"2466245524442CC82CD92CEA2CFB87B883AF839E838D1DB11DA196012DA091BC";
constant PM_Inst_RAM_Word4_INIT_0C : bit_vector(0 to 255) := x"F008067B066A0659164885B485A3859285812DF32DE24F1F5F0F2F1D2F0C2477";
constant PM_Inst_RAM_Word4_INIT_0D : bit_vector(0 to 255) := x"E0B22CB12CA12C912E88E082F45005BF05AE059D158C85B881AF819E818DC0A8";
constant PM_Inst_RAM_Word4_INIT_0E : bit_vector(0 to 255) := x"F40923880F04940E2F312F202D4C2D5D2D6E2D7F2D932D822CF12CE12CD12ECB";
constant PM_Inst_RAM_Word4_INIT_0F : bit_vector(0 to 255) := x"05B105A197004F5F4F4F4F3F5F2F2D2C2D3D2D4E2D5F81BC81AB819A8189C088";
constant PM_Inst_RAM_Word4_INIT_10 : bit_vector(0 to 255) := x"0739172885BD85AC859B858A095B094A09391928C00D2EB52EA42E932E82F029";
constant PM_Inst_RAM_Word4_INIT_11 : bit_vector(0 to 255) := x"2D932D82CFA71CF11CE11CD11CC194081C711C611C511C419408F059075B074A";
constant PM_Inst_RAM_Word4_INIT_12 : bit_vector(0 to 255) := x"2C6E2C5D2C4CC04CF4E123880E5B940EE03FEF2FEF1FEF0F2D7F2D6E2D5D2D4C";
constant PM_Inst_RAM_Word4_INIT_13 : bit_vector(0 to 255) := x"2D0C2D1D2D2E2D3F2D442D552D662D772D932D82087108610851084194082C7F";
constant PM_Inst_RAM_Word4_INIT_14 : bit_vector(0 to 255) := x"914D85BF85AEF30004BF04AE049D148C2CC42CD52CE62CF7F1A923880E5B940E";
constant PM_Inst_RAM_Word4_INIT_15 : bit_vector(0 to 255) := x"0E5B940E2D082D192D2A2D3B2D932D82F0510571056105511541917C916D915D";
constant PM_Inst_RAM_Word4_INIT_16 : bit_vector(0 to 255) := x"1CB11CA11C911C819408F06123FF85F982B382A28291828085FF85EEF0B92388";
constant PM_Inst_RAM_Word4_INIT_17 : bit_vector(0 to 255) := x"BFCDBE0FBFDE94F8B60F962FE080C001E081971392BC92AD929D928D2DB32DA2";
constant PM_Inst_RAM_Word4_INIT_18 : bit_vector(0 to 255) := x"904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F91DF91CF";
constant PM_Inst_RAM_Word4_INIT_19 : bit_vector(0 to 255) := x"9380E0B0E0A0E090E082032692100324921003219210032092109508902F903F";
constant PM_Inst_RAM_Word4_INIT_1A : bit_vector(0 to 255) := x"92100345938003469390E091E081033E9210032A93B0032993A0032893900327";
constant PM_Inst_RAM_Word4_INIT_1B : bit_vector(0 to 255) := x"9380E18A10059380E18910049380E18B95080365921003619380036293900349";
constant PM_Inst_RAM_Word4_INIT_1C : bit_vector(0 to 255) := x"1669940EE070E060E255E840E094E08B20109380E083037E9210037F92101006";
constant PM_Inst_RAM_Word4_INIT_1D : bit_vector(0 to 255) := x"E073E16BE093E287032F940EE14CE061E093E18B1895940EE070E660E094E08B";
constant PM_Inst_RAM_Word4_INIT_1E : bit_vector(0 to 255) := x"E073E267E093E4850D04940EE040E073E16BE093E287F43923880D04940EE041";
constant PM_Inst_RAM_Word4_INIT_1F : bit_vector(0 to 255) := x"E963E094E08BF03123880B3A940EE021E050E848E073E465E093E68107E3940E";
constant PM_Inst_RAM_Word4_INIT_20 : bit_vector(0 to 255) := x"E68120199380037D91800662940EE050E041E073E76DE093E6811895940EE070";
constant PM_Inst_RAM_Word4_INIT_21 : bit_vector(0 to 255) := x"E041E073E76DE093E68120189380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_22 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120179380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_23 : bit_vector(0 to 255) := x"E68120159380037D91800662940EE050E041E073E76DE093E68120169380037D";
constant PM_Inst_RAM_Word4_INIT_24 : bit_vector(0 to 255) := x"E041E073E76DE093E68120149380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_25 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120139380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_26 : bit_vector(0 to 255) := x"E68120219380037D91800662940EE050E041E073E76DE093E68120129380037D";
constant PM_Inst_RAM_Word4_INIT_27 : bit_vector(0 to 255) := x"E041E073E76DE093E68120209380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_28 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201F9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_29 : bit_vector(0 to 255) := x"E681201D9380037D91800662940EE050E041E073E76DE093E681201E9380037D";
constant PM_Inst_RAM_Word4_INIT_2A : bit_vector(0 to 255) := x"E041E073E76DE093E681201C9380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_2B : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681201B9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_2C : bit_vector(0 to 255) := x"E68120299380037D91800662940EE050E041E073E76DE093E681201A9380037D";
constant PM_Inst_RAM_Word4_INIT_2D : bit_vector(0 to 255) := x"E041E073E76DE093E68120289380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_2E : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120279380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_2F : bit_vector(0 to 255) := x"E68120259380037D91800662940EE050E041E073E76DE093E68120269380037D";
constant PM_Inst_RAM_Word4_INIT_30 : bit_vector(0 to 255) := x"E041E073E76DE093E68120249380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_31 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E68120239380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_32 : bit_vector(0 to 255) := x"E68120319380037D91800662940EE050E041E073E76DE093E68120229380037D";
constant PM_Inst_RAM_Word4_INIT_33 : bit_vector(0 to 255) := x"E041E073E76DE093E68120309380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_34 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202F9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_35 : bit_vector(0 to 255) := x"E681202D9380037D91800662940EE050E041E073E76DE093E681202E9380037D";
constant PM_Inst_RAM_Word4_INIT_36 : bit_vector(0 to 255) := x"E041E073E76DE093E681202C9380037D91800662940EE050E041E073E76DE093";
constant PM_Inst_RAM_Word4_INIT_37 : bit_vector(0 to 255) := x"91800662940EE050E041E073E76DE093E681202B9380037D91800662940EE050";
constant PM_Inst_RAM_Word4_INIT_38 : bit_vector(0 to 255) := x"E070EA65E094E08BF43031802F18931F95080573940EE093E681202A9380037D";
constant PM_Inst_RAM_Word4_INIT_39 : bit_vector(0 to 255) := x"972BB7DEB7CD93CF93DF9508911F1876940EE050E1402F61E094E08B1757940E";
constant PM_Inst_RAM_Word4_INIT_3A : bit_vector(0 to 255) := x"037E9210037F9210C175F0099706037F9190037E9180BFCDBE0FBFDE94F8B60F";
constant PM_Inst_RAM_Word4_INIT_3B : bit_vector(0 to 255) := x"2F5D2F4CE073E465E093E681F7E15081920D9001E08BE0F0E8E896112FBD2FAC";
constant PM_Inst_RAM_Word4_INIT_3C : bit_vector(0 to 255) := x"940EE093E681201891600AC1940EE093E681201991600B3A940EE5224F5F5F4F";
constant PM_Inst_RAM_Word4_INIT_3D : bit_vector(0 to 255) := x"E681201591600AC1940EE093E681201691600AC1940EE093E681201791600AC1";
constant PM_Inst_RAM_Word4_INIT_3E : bit_vector(0 to 255) := x"91600AC1940EE093E681201391600AC1940EE093E681201491600AC1940EE093";
constant PM_Inst_RAM_Word4_INIT_3F : bit_vector(0 to 255) := x"940EE093E681202091600AC1940EE093E681202191600AC1940EE093E6812012";
-- BRAM 0 in address space [0x00002800:0x00002FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word5 LOC = RAMB16_X0Y7;
constant PM_Inst_RAM_Word5_INIT_00 : bit_vector(0 to 255) := x"E681201D91600AC1940EE093E681201E91600AC1940EE093E681201F91600AC1";
constant PM_Inst_RAM_Word5_INIT_01 : bit_vector(0 to 255) := x"91600AC1940EE093E681201B91600AC1940EE093E681201C91600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_02 : bit_vector(0 to 255) := x"940EE093E681202891600AC1940EE093E681202991600AC1940EE093E681201A";
constant PM_Inst_RAM_Word5_INIT_03 : bit_vector(0 to 255) := x"E681202591600AC1940EE093E681202691600AC1940EE093E681202791600AC1";
constant PM_Inst_RAM_Word5_INIT_04 : bit_vector(0 to 255) := x"91600AC1940EE093E681202391600AC1940EE093E681202491600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_05 : bit_vector(0 to 255) := x"940EE093E681203091600AC1940EE093E681203191600AC1940EE093E6812022";
constant PM_Inst_RAM_Word5_INIT_06 : bit_vector(0 to 255) := x"E681202D91600AC1940EE093E681202E91600AC1940EE093E681202F91600AC1";
constant PM_Inst_RAM_Word5_INIT_07 : bit_vector(0 to 255) := x"91600AC1940EE093E681202B91600AC1940EE093E681202C91600AC1940EE093";
constant PM_Inst_RAM_Word5_INIT_08 : bit_vector(0 to 255) := x"91801388940E201A91801895940EE070EA67E094E08B0AC1940EE093E681202A";
constant PM_Inst_RAM_Word5_INIT_09 : bit_vector(0 to 255) := x"91801388940E201E91801388940E201D91801388940E201C91801388940E201B";
constant PM_Inst_RAM_Word5_INIT_0A : bit_vector(0 to 255) := x"940EE070EB6CE094E08B1388940E202191801388940E202091801388940E201F";
constant PM_Inst_RAM_Word5_INIT_0B : bit_vector(0 to 255) := x"940E201591801388940E201491801388940E201391801388940E201291801895";
constant PM_Inst_RAM_Word5_INIT_0C : bit_vector(0 to 255) := x"940E201991801388940E201891801388940E201791801388940E201691801388";
constant PM_Inst_RAM_Word5_INIT_0D : bit_vector(0 to 255) := x"91801388940E202B91801388940E202A91801895940EE070ED61E094E08B1388";
constant PM_Inst_RAM_Word5_INIT_0E : bit_vector(0 to 255) := x"91801388940E202F91801388940E202E91801388940E202D91801388940E202C";
constant PM_Inst_RAM_Word5_INIT_0F : bit_vector(0 to 255) := x"940E202291801895940EE070EE65E094E08B1388940E203191801388940E2030";
constant PM_Inst_RAM_Word5_INIT_10 : bit_vector(0 to 255) := x"940E202691801388940E202591801388940E202491801388940E202391801388";
constant PM_Inst_RAM_Word5_INIT_11 : bit_vector(0 to 255) := x"940EE093E6811388940E202991801388940E202891801388940E202791801388";
constant PM_Inst_RAM_Word5_INIT_12 : bit_vector(0 to 255) := x"1591940EE090E080E077ED60037E9380037F93909601037F9190037E91800573";
constant PM_Inst_RAM_Word5_INIT_13 : bit_vector(0 to 255) := x"933F932F2411920FB60F920F921F950891DF91CFBFCDBE0FBFDE94F8B60F962B";
constant PM_Inst_RAM_Word5_INIT_14 : bit_vector(0 to 255) := x"1DA1960103889130038791B0038691A0038591900384918093BF93AF939F938F";
constant PM_Inst_RAM_Word5_INIT_15 : bit_vector(0 to 255) := x"93A00385939003849380038893201DB11DA19601572DF020372D5F2D2F231DB1";
constant PM_Inst_RAM_Word5_INIT_16 : bit_vector(0 to 255) := x"038093801DB11DA19601038391B0038291A00381919003809180038793B00386";
constant PM_Inst_RAM_Word5_INIT_17 : bit_vector(0 to 255) := x"901F900FBE0F900F912F913F918F919F91AF91BF038393B0038293A003819390";
constant PM_Inst_RAM_Word5_INIT_18 : bit_vector(0 to 255) := x"2F952F842F732F62BF8F0387915003869140038591300384912094F8B78F9518";
constant PM_Inst_RAM_Word5_INIT_19 : bit_vector(0 to 255) := x"9160038591500384914094F8B78F2F192F082EF72EE6931F930F92FF92EF9508";
constant PM_Inst_RAM_Word5_INIT_1A : bit_vector(0 to 255) := x"1B84BF2F038791B0038691A0038591900384918094F8B72FBF8F038791700386";
constant PM_Inst_RAM_Word5_INIT_1B : bit_vector(0 to 255) := x"6084B7839478950890EF90FF910F911FF760071B070A06F916E80BB70BA60B95";
constant PM_Inst_RAM_Word5_INIT_1C : bit_vector(0 to 255) := x"BD856082B585BD8F6081B58FBD8E6081B58EBD8E6082B58EBF876081B787BF83";
constant PM_Inst_RAM_Word5_INIT_1D : bit_vector(0 to 255) := x"4F3F56262D9095C82FF92FE84F9F53862F932F82E0302F289508BD856081B585";
constant PM_Inst_RAM_Word5_INIT_1E : bit_vector(0 to 255) := x"95C896312DA095C84FFF59E01FFF0FEEE0F02FE8F0A923882D8095C82FF32FE2";
constant PM_Inst_RAM_Word5_INIT_1F : bit_vector(0 to 255) := x"2F952F84E0502F489508938C2B89918C9508938C23899590918CF42923662DB0";
constant PM_Inst_RAM_Word5_INIT_20 : bit_vector(0 to 255) := x"4F5F56462D9095C82FF92FE84F9F53862F952F842D2095C82FF92FE84F9F5086";
constant PM_Inst_RAM_Word5_INIT_21 : bit_vector(0 to 255) := x"B58FF4213024C004778FB58FF4193023F0B12322F16923332D3095C82FF52FE4";
constant PM_Inst_RAM_Word5_INIT_22 : bit_vector(0 to 255) := x"E0F02FE3BD857D8FB585F4193025C005BF837D8FB783F4213021C00BBD8F7D8F";
constant PM_Inst_RAM_Word5_INIT_23 : bit_vector(0 to 255) := x"9508938C23899590918CF42923662DB095C896312DA095C84FFF58E21FFF0FEE";
constant PM_Inst_RAM_Word5_INIT_24 : bit_vector(0 to 255) := x"91E0B12C93FF93EF939F938F932F2411920FB60F920F921F9508938C2B89918C";
constant PM_Inst_RAM_Word5_INIT_25 : bit_vector(0 to 255) := x"91FF0409939083204FFC57E7E0F0F0311798040A918050E1779F2F9E5FEF0409";
constant PM_Inst_RAM_Word5_INIT_26 : bit_vector(0 to 255) := x"2F242F192F08931F930F92FF92EF9518901F900FBE0F900F912F918F919F91EF";
constant PM_Inst_RAM_Word5_INIT_27 : bit_vector(0 to 255) := x"502118E4940EE090E18EE874E860971590FC90ED96142FB92FA82F572F462F35";
constant PM_Inst_RAM_Word5_INIT_28 : bit_vector(0 to 255) := x"83202DFF2DEE18E4940EE050E040E030E0222F622F732F842F95405040404030";
constant PM_Inst_RAM_Word5_INIT_29 : bit_vector(0 to 255) := x"0F88C002971C900C961C2F952F84E050E0418120971791FC91ED96162FB12FA0";
constant PM_Inst_RAM_Word5_INIT_2A : bit_vector(0 to 255) := x"C002971D900C961D2F952F848120971791FC91ED961683202B28F7E2940A1F99";
constant PM_Inst_RAM_Word5_INIT_2B : bit_vector(0 to 255) := x"1F550F44C002900C961E8180971791FC91ED961683202B28F7E2940A1F990F88";
constant PM_Inst_RAM_Word5_INIT_2C : bit_vector(0 to 255) := x"E090918C852785B185A02FF92FE8950890EF90FF910F911F83802B84F7E2940A";
constant PM_Inst_RAM_Word5_INIT_2D : bit_vector(0 to 255) := x"9390E091E08B950883602DE085F38402CFF6FF80F7E2940A95879595C0022E02";
constant PM_Inst_RAM_Word5_INIT_2E : bit_vector(0 to 255) := x"E28A040F938004109390E090E289040D9380040E9390E093E889040B9380040C";
constant PM_Inst_RAM_Word5_INIT_2F : bit_vector(0 to 255) := x"938004169390E090E28C0413938004149390E090E28B0411938004129390E090";
constant PM_Inst_RAM_Word5_INIT_30 : bit_vector(0 to 255) := x"15BD940E9508041A9380E08504199380E08704189380E08304179380E0840415";
constant PM_Inst_RAM_Word5_INIT_31 : bit_vector(0 to 255) := x"2FA09621C00B2FD72FC62F192F0893DF93CF931F930FCFFD139B940E11B8940E";
constant PM_Inst_RAM_Word5_INIT_32 : bit_vector(0 to 255) := x"910F911F91CF91DFF7912366816895092F912F802DE081F0900191FC91ED2FB1";
constant PM_Inst_RAM_Word5_INIT_33 : bit_vector(0 to 255) := x"2DBF2DAEC0102FD52FC42EF72EE62F192F0893DF93CF931F930F92FF92EF9508";
constant PM_Inst_RAM_Word5_INIT_34 : bit_vector(0 to 255) := x"F7719720972195092F912F802DE081F0900191FC91ED2FB12FA02EFB2EEA916D";
constant PM_Inst_RAM_Word5_INIT_35 : bit_vector(0 to 255) := x"950895092DE081F3800291FC91ED2FB92FA8950890EF90FF910F911F91CF91DF";
constant PM_Inst_RAM_Word5_INIT_36 : bit_vector(0 to 255) := x"931F930F92FF92EF92DF92CF92BF92AF929F928F927F926F925F924F923F922F";
constant PM_Inst_RAM_Word5_INIT_37 : bit_vector(0 to 255) := x"2EF72EE62ED52EC42E392E28BFCDBE0FBFDE94F8B60F97A0B7DEB7CD93CF93DF";
constant PM_Inst_RAM_Word5_INIT_38 : bit_vector(0 to 255) := x"24992488C06A1821940EE030E020E070E060E050E340F4490571056105511541";
constant PM_Inst_RAM_Word5_INIT_39 : bit_vector(0 to 255) := x"2D6C2D7D2D8E2D9F1D190D081F1D0F0CE010E0012477246624552E4224BB24AA";
constant PM_Inst_RAM_Word5_INIT_3A : bit_vector(0 to 255) := x"2D8E2D9F1CB11CA11C911C81940883602FF12FE018BD940E2D242D352D462D57";
constant PM_Inst_RAM_Word5_INIT_3B : bit_vector(0 to 255) := x"2EFB2EEA2ED92EC82FB52FA42F932F8218BD940E2D242D352D462D572D6C2D7D";
constant PM_Inst_RAM_Word5_INIT_3C : bit_vector(0 to 255) := x"1C6194082E7D2E6C1CF90CE81EFD0EEC2CF12EE8E081F68904F104E104D114C1";
constant PM_Inst_RAM_Word5_INIT_3D : bit_vector(0 to 255) := x"0DEE2DFD2DECC01808D918C82ED92EC809B109A197012D882D992DAA2DBB1C71";
constant PM_Inst_RAM_Word5_INIT_3E : bit_vector(0 to 255) := x"E030E0202D932D822F752F659550FD4727555C49C0015D40F410304A81401DFF";
constant PM_Inst_RAM_Word5_INIT_3F : bit_vector(0 to 255) := x"91DF91CFBFCDBE0FBFDE94F8B60F96A0F729047F146E08F108E194081821940E";
-- BRAM 0 in address space [0x00003000:0x000037FF], bit lane [15:0]
-- INST PM_Inst/RAM_Word6 LOC = RAMB16_X0Y5;
constant PM_Inst_RAM_Word6_INIT_00 : bit_vector(0 to 255) := x"902F903F904F905F906F907F908F909F90AF90BF90CF90DF90EF90FF910F911F";
constant PM_Inst_RAM_Word6_INIT_01 : bit_vector(0 to 255) := x"1760940E950895092F642DE081F0900191FC91EDF441053115212FB92FA89508";
constant PM_Inst_RAM_Word6_INIT_02 : bit_vector(0 to 255) := x"F441053115212F172F062EF52EE42FD92FC893DF93CF931F930F92FF92EF9508";
constant PM_Inst_RAM_Word6_INIT_03 : bit_vector(0 to 255) := x"E060E050E24DC010FF77F4C90531302AC01E95092F642DE081F0900181F981E8";
constant PM_Inst_RAM_Word6_INIT_04 : bit_vector(0 to 255) := x"2F712F9D2F8C1D111D011CF11CE194E094F0950095101821940EE030E020E070";
constant PM_Inst_RAM_Word6_INIT_05 : bit_vector(0 to 255) := x"2F08931F930F950890EF90FF910F911F91CF91DF1760940EE02A2D4E2D5F2F60";
constant PM_Inst_RAM_Word6_INIT_06 : bit_vector(0 to 255) := x"E020E070E060E050E04A2F912F801821940EE030E020E070E060E050E04D2F19";
constant PM_Inst_RAM_Word6_INIT_07 : bit_vector(0 to 255) := x"2F352F242F192F08931F930F92FF92EF92DF92CF9508910F911F1821940EE030";
constant PM_Inst_RAM_Word6_INIT_08 : bit_vector(0 to 255) := x"910F911F185D940E2F912F801811940E2D4C2D5D2D6E2D7F24FF24EE24DD2EC6";
constant PM_Inst_RAM_Word6_INIT_09 : bit_vector(0 to 255) := x"911F185D940E2F912F801757940E2F192F08931F930F950890CF90DF90EF90FF";
constant PM_Inst_RAM_Word6_INIT_0A : bit_vector(0 to 255) := x"1F551F441F330F221FF51FE41FB30FA2C004FF6027AA27BB27EE27FF9508910F";
constant PM_Inst_RAM_Word6_INIT_0B : bit_vector(0 to 255) := x"1BAA2E1AE2A195082F6A2F7B2F8E2F9FF77107769700F7899567957795879596";
constant PM_Inst_RAM_Word6_INIT_0C : bit_vector(0 to 255) := x"0BE40BB31BA2F02007F507E407B317A21FFF1FEE1FBB1FAAC00D2FFB2FEA1BBB";
constant PM_Inst_RAM_Word6_INIT_0D : bit_vector(0 to 255) := x"2F6A2F592F482F372F269590958095709560F769941A1F991F881F771F660BF5";
constant PM_Inst_RAM_Word6_INIT_0E : bit_vector(0 to 255) := x"95409550F4381C00D00ADFD2D004FD57D00E26052E09FB9795082F9F2F8E2F7B";
constant PM_Inst_RAM_Word6_INIT_0F : bit_vector(0 to 255) := x"0FEE95084F9F4F8F4F7F9561957095809590F7F695084F5F4F4F4F3F95219530";
constant PM_Inst_RAM_Word6_INIT_10 : bit_vector(0 to 255) := x"6944205241542073692073696854CFFF94F89508920F95C8920F963195C81FFF";
constant PM_Inst_RAM_Word6_INIT_11 : bit_vector(0 to 255) := x"50554B43414200656369766564207265746E756F63206C616E6769732065646F";
constant PM_Inst_RAM_Word6_INIT_12 : bit_vector(0 to 255) := x"632065746972570030005458542E50554B4341422064656E65704F005458542E";
constant PM_Inst_RAM_Word6_INIT_13 : bit_vector(0 to 255) := x"552D3770557265746E756F6320657469725700306E442D376E447265746E756F";
constant PM_Inst_RAM_Word6_INIT_14 : bit_vector(0 to 255) := x"63695420657469725700306E442D376E4472656B636954206574697257003070";
constant PM_Inst_RAM_Word6_INIT_15 : bit_vector(0 to 255) := x"1516C90000000017310AB20AC100000000FFFFFFFF003070552D37705572656B";
constant PM_Inst_RAM_Word6_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000173117";
constant PM_Inst_RAM_Word6_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word6_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
-- BRAM 0 in address space [0x00003800:0x00003FFF], bit lane [15:0]
-- INST PM_Inst/RAM_Word7 LOC = RAMB16_X0Y6;
constant PM_Inst_RAM_Word7_INIT_00 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_01 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_02 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_03 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_04 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_05 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_06 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_07 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_08 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_09 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_0F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_10 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_11 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_12 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_13 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_14 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_15 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_16 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_17 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_18 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_19 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_1F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_20 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_21 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_22 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_23 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_24 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_25 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_26 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_27 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_28 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_29 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_2F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_30 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_31 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_32 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_33 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_34 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_35 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_36 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_37 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_38 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_39 : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3A : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3B : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3C : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3D : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3E : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
constant PM_Inst_RAM_Word7_INIT_3F : bit_vector(0 to 255) := x"0000000000000000000000000000000000000000000000000000000000000000";
end prog_mem_init_pkg;

74
src/AVR8/uC/AVR8.vhd
View File

@ -29,15 +29,18 @@ use WORK.AVR_uC_CompPack.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.XMemCompPack.all; -- Xilinx RAM components
use WORK.spi_mod_comp_pack.all; --SPI
use WORK.spi_slv_sel_comp_pack.all;
use WORK.MemAccessCtrlPack.all;
use WORK.MemAccessCompPack.all;
entity AVR8 is port(
entity AVR8 is
generic (
CDATAMEMSIZE : integer;
CPROGMEMSIZE : integer
);
port (
nrst : in std_logic; --Uncomment this to connect reset to an external pushbutton. Must be defined in ucf.
clk16M : in std_logic;
portaout : out std_logic_vector(7 downto 0);
@ -78,31 +81,6 @@ constant CImplSPI : boolean := FALSE; -- adding SPI master
constant CImplTmrCnt : boolean := FALSE; --AVR8 Timer
constant CImplExtIRQ : boolean := FALSE; --AVR8 Interrupt Unit
component XDM2Kx8 port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CDATAMEMSIZE downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end component;
component XPM9Kx16 port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CPROGMEMSIZE downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
we : in std_logic
);
end component;
-- ############################## Define Components for User Cores ##################################################
-- ###############################################################################################################
-- ############################## Signals connected directly to the core ##########################################
@ -773,26 +751,34 @@ end generate;
ram_cp2_n <= not clk16M;
---- Data memory(8-bit)
DRAM_Inst:component XDM2Kx8
DM_Inst : entity work.XDM
generic map (
WIDTH => 8,
SIZE => CDATAMEMSIZE
)
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => mem_ramadr(CDATAMEMSIZE downto 0),
din => mem_ram_dbus_in,
dout => mem_ram_dbus_out,
we => ram_ramwe
);
cp2 => ram_cp2_n,
ce => vcc,
address => mem_ramadr(f_log2(CDATAMEMSIZE) - 1 downto 0),
din => mem_ram_dbus_in,
dout => mem_ram_dbus_out,
we => ram_ramwe
);
-- Program memory
PM_Inst:component XPM9Kx16
PM_Inst : entity work.XPM
generic map (
WIDTH => 16,
SIZE => CPROGMEMSIZE
)
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => pm_adr(CPROGMEMSIZE downto 0),
din => pm_din,
dout => pm_dout,
we => pm_l_we
);
cp2 => ram_cp2_n,
ce => vcc,
address => pm_adr(f_log2(CPROGMEMSIZE) - 1 downto 0),
din => pm_din,
dout => pm_dout,
we => pm_l_we
);
-- ********************** JTAG and memory **********************************************

38
src/AtomBusMon.bmm
View File

@ -2,37 +2,37 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
END_BUS_BLOCK;
mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

6
src/AtomBusMon.vhd
View File

@ -77,7 +77,11 @@ begin
CLK2X_OUT => open
);
mon : entity work.BusMonCore port map (
mon : entity work.BusMonCore
generic map (
avr_prog_mem_size => 1024 * 8
)
port map (
clock_avr => clock_avr,
busmon_clk => Phi2,
busmon_clken => '1',

42
src/AtomCpuMon.bmm
View File

@ -1,42 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
END_BUS_BLOCK;
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word8 [15:0];
END_BUS_BLOCK;
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

5
src/AtomCpuMon.vhd
View File

@ -104,8 +104,9 @@ begin
core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
avr_prog_mem_size => 1024 * 8
)
port map (
clock_avr => clock_avr,

42
src/AtomFast6502.bmm
View File

@ -1,42 +1,38 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
END_BUS_BLOCK;
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Word8 [15:0];
END_BUS_BLOCK;
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

5
src/AtomFast6502.vhd
View File

@ -136,8 +136,9 @@ begin
core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
avr_prog_mem_size => 1024 * 8
)
port map (
clock_avr => clock_avr,

16
src/BusMonCore.vhd
View File

@ -24,9 +24,11 @@ use work.OhoPack.all ;
entity BusMonCore is
generic (
num_comparators : integer := 8;
reg_width : integer := 46;
fifo_width : integer := 72
num_comparators : integer := 8;
reg_width : integer := 46;
fifo_width : integer := 72;
avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
avr_prog_mem_size : integer := 1024 * 8 -- Default is 8K, 6809 amd Z80 need 9K
);
port (
clock_avr : in std_logic;
@ -178,9 +180,13 @@ begin
dy_ser => tcclk,
dy_rclk => tmosi
);
Inst_AVR8: entity work.AVR8 port map(
Inst_AVR8: entity work.AVR8
generic map(
CDATAMEMSIZE => avr_data_mem_size,
CPROGMEMSIZE => avr_prog_mem_size
)
port map(
clk16M => clock_avr,
nrst => nrst_avr,

44
src/MC6809ECpuMon.bmm
View File

@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word8 [15:0];
END_BUS_BLOCK;
mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

3
src/MC6809ECpuMon.vhd
View File

@ -162,7 +162,8 @@ begin
mon : entity work.BusMonCore
generic map (
num_comparators => 8
num_comparators => 8,
avr_prog_mem_size => 1024 * 9
)
port map (
clock_avr => clock_avr,

15
src/MOS6502CpuMonCore.vhd
View File

@ -23,9 +23,11 @@ use work.OhoPack.all ;
entity MOS6502CpuMonCore is
generic (
UseT65Core : boolean;
UseAlanDCore : boolean
);
UseT65Core : boolean;
UseAlanDCore : boolean;
avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
avr_prog_mem_size : integer := 1024 * 8 -- 6502 fits in 8K, others need 9K
);
port (
clock_avr : in std_logic;
@ -104,7 +106,12 @@ architecture behavioral of MOS6502CpuMonCore is
begin
mon : entity work.BusMonCore port map (
mon : entity work.BusMonCore
generic map (
avr_data_mem_size => avr_data_mem_size,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => busmon_clken,

17
src/XPM_Generic.bmm Normal file
View File

@ -0,0 +1,17 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/mon/Inst_AVR8/PM_Inst/Mram_RAM8 [15:14];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM7 [13:12];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM6 [11:10];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM5 [ 9: 8];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM4 [ 7: 6];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM3 [ 5: 4];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM2 [ 3: 2];
core/mon/Inst_AVR8/PM_Inst/Mram_RAM1 [ 1: 0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

44
src/Z80CpuMon.bmm
View File

@ -2,41 +2,41 @@ ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_code RAMB16 [0x00000000:0x000047ff]
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word0 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word1 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[0].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word2 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[1].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word3 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word4 [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word5 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[2].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word6 [15:0];
mon/Inst_AVR8/PM_Inst/RAM_Inst[3].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word7 [15:0];
END_BUS_BLOCK;
mon/Inst_AVR8/PM_Inst/RAM_Inst[4].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Word8 [15:0];
END_BUS_BLOCK;
mon/Inst_AVR8/PM_Inst/RAM_Inst[5].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[6].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[7].Ram [15:0];
END_BUS_BLOCK;
BUS_BLOCK
mon/Inst_AVR8/PM_Inst/RAM_Inst[8].Ram [15:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;

3
src/Z80CpuMon.vhd
View File

@ -152,7 +152,8 @@ begin
mon : entity work.BusMonCore
generic map (
num_comparators => 4
num_comparators => 4,
avr_prog_mem_size => 1024 * 9
)
port map (
clock_avr => clock_avr,