David Banks
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344e03185d
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Reworked the 6502 single stepping to hide the fact that register writes are pipelined
Change-Id: I6d9157e3d9ade9af72e11d255b224cc7f210f376
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2015-10-26 16:44:25 +00:00 |
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David Banks
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9c4b9aa944
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In ICE-T65 fixed the timing of ICE initiated read/write cycles to give them a whole cycle
Change-Id: I6bfdf624ad4340a219096f231334ec8a9bbfc5af
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2015-10-26 12:54:17 +00:00 |
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David Banks
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318f7678a3
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Further optimization of static data in disassemlers, data memory usage < 1K, version now 0.61
Change-Id: Ibcb5fd3e9141022cb940ebc70ca5369bdeb738c4
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2015-07-07 16:20:32 +01:00 |
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David Banks
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d6c9287067
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Changed to 18K ROM/2K RAM, version now 0.60, bitfiles published for all three designs
Change-Id: I2dd2b203e68d3ddde7d8bbb9052d4d46b802fbbb
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2015-07-06 18:49:57 +01:00 |
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David Banks
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eec6e10440
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Added option to do repeat a read/write command n times (where n can be large), incremented version to 0.37
Change-Id: I4b1b02e8d67a581acbf4d5b044e86ffb2bc7e27e
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2015-06-22 18:11:11 +01:00 |
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David Banks
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5322c18443
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Fixed a bug in the logging of memory errors; incremented version to 0.35
Change-Id: I6cc34881abe359bfe2cc8ae5e84fb2296c49096a
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2015-06-20 16:56:56 +01:00 |
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David Banks
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68f6dccf89
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Added crc and memory test commands, incremented version to 0.34
Change-Id: Ib259fcfce3f10b109d6b9606da3c28cb47230196
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2015-06-20 16:41:40 +01:00 |
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David Banks
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14e4adda94
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Implemented cycle counter and data bus monitoring during read/write watches/breakpoints, incremented version to 0.32
Change-Id: I408f57e66800ea58a56896ec4af5d815d1f12c34
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2015-06-20 12:30:18 +01:00 |
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David Banks
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35ad735420
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Added a jumper enabled fakeTube register at 0xFEE0 with value 0xFE to work around a beeb issue with pullups, incremented version to 0.28
Change-Id: I6b7b79cb01aa350b0caca27e75fb9c689558bcec
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2015-06-18 11:01:06 +01:00 |
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David Banks
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35f8b5419a
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Added bitfiles for Roland to test
Change-Id: I03471403aefa0702f7f758c73247a75118a5fb05
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2015-06-18 07:52:10 +01:00 |
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