692 lines
25 KiB
VHDL
692 lines
25 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : BusMonCore.vhd
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-- /___/ /\ Timestamp : 30/05/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: AtomBusMon
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--Device: XC3S250E
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.OhoPack.all ;
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entity BusMonCore is
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generic (
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num_comparators : integer := 8;
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reg_width : integer := 46;
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fifo_width : integer := 72;
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avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
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avr_prog_mem_size : integer := 1024 * 8 -- Default is 8K, 6809 amd Z80 need 9K
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);
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port (
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clock_avr : in std_logic;
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busmon_clk : in std_logic;
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busmon_clken : in std_logic;
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cpu_clk : in std_logic;
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cpu_clken : in std_logic;
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-- CPU Signals
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Addr : in std_logic_vector(15 downto 0);
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Data : in std_logic_vector(7 downto 0);
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Rd_n : in std_logic;
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Wr_n : in std_logic;
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RdIO_n : in std_logic;
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WrIO_n : in std_logic;
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Sync : in std_logic;
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Rdy : out std_logic;
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nRSTin : in std_logic;
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nRSTout : out std_logic;
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CountCycle : in std_logic;
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-- CPU Registers
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-- unused in pure bus monitor mode
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Regs : in std_logic_vector(255 downto 0);
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-- CPI Specific data
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PdcData : in std_logic_vector(7 downto 0) := x"00";
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-- CPU Memory Read/Write
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-- unused in pure bus monitor mode
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RdMemOut : out std_logic;
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WrMemOut : out std_logic;
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RdIOOut : out std_logic;
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WrIOOut : out std_logic;
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ExecOut : out std_logic;
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AddrOut : out std_logic_vector(15 downto 0);
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DataOut : out std_logic_vector(7 downto 0);
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DataIn : in std_logic_vector(7 downto 0);
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Done : in std_logic;
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-- External Interrupt Control
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int_ctrl : out std_logic_vector(7 downto 0) := x"00";
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-- Single Step interface
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SS_Single : out std_logic;
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SS_Step : out std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- AVR Serial Port
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- Switches
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sw_reset_cpu : in std_logic;
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sw_reset_avr : in std_logic;
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-- LEDs
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led_bkpt : out std_logic;
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led_trig0 : out std_logic;
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led_trig1 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic
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);
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end BusMonCore;
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architecture behavioral of BusMonCore is
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signal cpu_reset_n : std_logic;
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signal nrst_avr : std_logic;
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signal nrst1 : std_logic;
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signal nrst2 : std_logic;
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signal nrst3 : std_logic;
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-- debounce time is 2^17 / 16MHz = 8.192ms
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signal nrst_counter : unsigned(17 downto 0);
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signal dy_counter : std_logic_vector(31 downto 0);
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signal dy_data : y2d_type ;
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signal mux : std_logic_vector(7 downto 0);
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signal muxsel : std_logic_vector(5 downto 0);
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signal cmd_edge : std_logic;
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signal cmd_edge1 : std_logic;
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signal cmd_edge2 : std_logic;
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signal cmd_ack : std_logic;
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signal cmd_ack1 : std_logic;
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signal cmd_ack2 : std_logic;
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signal cmd : std_logic_vector(5 downto 0);
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signal addr_sync : std_logic_vector(15 downto 0);
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signal addr_inst : std_logic_vector(15 downto 0);
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signal Addr1 : std_logic_vector(15 downto 0);
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signal Data1 : std_logic_vector(7 downto 0);
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signal ext_clk : std_logic;
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signal timer0Count : std_logic_vector(23 downto 0);
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signal timer1Count : std_logic_vector(23 downto 0);
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signal cycleCount : std_logic_vector(23 downto 0);
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signal instrCount : std_logic_vector(23 downto 0);
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signal single : std_logic;
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signal reset : std_logic;
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signal step : std_logic;
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signal bw_status : std_logic_vector(3 downto 0);
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signal bw_status1 : std_logic_vector(3 downto 0);
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signal auto_inc : std_logic;
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signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
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signal brkpt_enable : std_logic;
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signal brkpt_active : std_logic;
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signal brkpt_active1 : std_logic;
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signal watch_active : std_logic;
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signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
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signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
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signal fifo_empty : std_logic;
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signal fifo_full : std_logic;
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signal fifo_not_empty1 : std_logic;
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signal fifo_not_empty2 : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_rd_en : std_logic;
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signal fifo_wr : std_logic;
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signal fifo_wr_en : std_logic;
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signal fifo_rst : std_logic;
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signal memory_rd : std_logic;
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signal memory_wr : std_logic;
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signal io_rd : std_logic;
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signal io_wr : std_logic;
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signal exec : std_logic;
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signal addr_dout_reg : std_logic_vector(23 downto 0);
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signal din_reg : std_logic_vector(7 downto 0);
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signal Rdy_int : std_logic;
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signal unused_d6 : std_logic;
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signal unused_d7 : std_logic;
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signal last_done : std_logic;
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signal cmd_done : std_logic;
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signal reset_counter : std_logic_vector(9 downto 0);
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signal dropped_counter : std_logic_vector(3 downto 0);
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signal timer_mode : std_logic_vector(1 downto 0);
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begin
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inst_oho_dy1 : entity work.Oho_Dy1 port map (
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dy_clock => clock_avr,
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dy_rst_n => '1',
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dy_data => dy_data,
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dy_update => '1',
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dy_frame => open,
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dy_frameend => open,
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dy_frameend_c => open,
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dy_pwm => "1010",
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dy_counter => dy_counter,
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dy_sclk => tdin,
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dy_ser => tcclk,
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dy_rclk => tmosi
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);
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Inst_AVR8: entity work.AVR8
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generic map(
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CDATAMEMSIZE => avr_data_mem_size,
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CPROGMEMSIZE => avr_prog_mem_size
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)
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port map(
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clk16M => clock_avr,
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nrst => nrst_avr,
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portain => PdcData,
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portaout => open,
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-- Command Port
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portbin(0) => '0',
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portbin(1) => '0',
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portbin(2) => '0',
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portbin(3) => '0',
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portbin(4) => '0',
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portbin(5) => '0',
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portbin(6) => '0',
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portbin(7) => '0',
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portbout(0) => cmd(0),
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portbout(1) => cmd(1),
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portbout(2) => cmd(2),
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portbout(3) => cmd(3),
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portbout(4) => cmd(4),
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portbout(5) => cmd(5),
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portbout(6) => cmd_edge,
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portbout(7) => open,
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-- Status Port
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portdin(0) => '0',
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portdin(1) => '0',
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portdin(2) => '0',
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portdin(3) => '0',
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portdin(4) => '0',
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portdin(5) => '0',
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portdin(6) => cmd_ack2,
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portdin(7) => fifo_not_empty2,
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portdout(0) => muxsel(0),
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portdout(1) => muxsel(1),
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portdout(2) => muxsel(2),
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portdout(3) => muxsel(3),
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portdout(4) => muxsel(4),
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portdout(5) => muxsel(5),
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portdout(6) => unused_d6,
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portdout(7) => unused_d7,
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-- Mux Port
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portein => mux,
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porteout => open,
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spi_mosio => open,
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spi_scko => open,
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spi_misoi => '0',
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rxd => avr_RxD,
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txd => avr_TxD
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);
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-- Syncronise signals crossing busmon_clk / clock_avr boundary
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process (clock_avr)
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begin
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if rising_edge(clock_avr) then
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fifo_not_empty1 <= not fifo_empty;
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fifo_not_empty2 <= fifo_not_empty1;
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cmd_ack1 <= cmd_ack;
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cmd_ack2 <= cmd_ack1;
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end if;
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end process;
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WatchEvents_inst : entity work.WatchEvents port map(
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clk => busmon_clk,
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srst => fifo_rst,
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din => fifo_din,
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wr_en => fifo_wr_en,
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rd_en => fifo_rd_en,
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dout => fifo_dout,
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full => fifo_full,
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empty => fifo_empty
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);
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fifo_wr_en <= fifo_wr and busmon_clken;
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fifo_rd_en <= fifo_rd and busmon_clken;
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-- The fifo is writen the cycle after the break point
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-- Addr1 is the address bus delayed by 1 cycle
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-- DataWr1 is the data being written delayed by 1 cycle
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-- DataRd is the data being read, that is already one cycle late
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-- bw_state1(1) is 1 for writes, and 0 for reads
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fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
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-- Implement a 4-bit saturating counter of the number of dropped events
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process (busmon_clk)
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begin
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if rising_edge(busmon_clk) then
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if busmon_clken = '1' then
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if fifo_rst = '1' then
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dropped_counter <= x"0";
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elsif fifo_wr_en = '1' then
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if fifo_full = '1' then
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if dropped_counter /= x"F" then
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dropped_counter <= dropped_counter + 1;
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end if;
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else
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dropped_counter <= x"0";
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end if;
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end if;
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end if;
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end if;
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end process;
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led_trig0 <= trig(0);
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led_trig1 <= trig(1);
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led_bkpt <= brkpt_active;
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nrst_avr <= not sw_reset_avr;
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-- OHO DY1 Display for Testing
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dy_data(0) <= hex & "0000" & Addr(3 downto 0);
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dy_data(1) <= hex & "0000" & Addr(7 downto 4);
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dy_data(2) <= hex & "0000" & "00" & sw_reset_avr & sw_reset_cpu;
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mux <= addr_inst(7 downto 0) when muxsel = 0 else
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addr_inst(15 downto 8) when muxsel = 1 else
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din_reg when muxsel = 2 else
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instrCount(23 downto 16) when muxsel = 3 else
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instrCount(7 downto 0) when muxsel = 4 else
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instrCount(15 downto 8) when muxsel = 5 else
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fifo_dout(7 downto 0) when muxsel = 6 else
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fifo_dout(15 downto 8) when muxsel = 7 else
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fifo_dout(23 downto 16) when muxsel = 8 else
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fifo_dout(31 downto 24) when muxsel = 9 else
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fifo_dout(39 downto 32) when muxsel = 10 else
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fifo_dout(47 downto 40) when muxsel = 11 else
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fifo_dout(55 downto 48) when muxsel = 12 else
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fifo_dout(63 downto 56) when muxsel = 13 else
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fifo_dout(71 downto 64) when muxsel = 14 else
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Regs(8 * to_integer(unsigned(muxsel(4 downto 0))) + 7 downto 8 * to_integer(unsigned(muxsel(4 downto 0))));
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-- Combinatorial set of comparators to decode breakpoint/watch addresses
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brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n, trig)
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variable i : integer;
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variable reg_addr : std_logic_vector(15 downto 0);
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variable reg_mask : std_logic_vector(15 downto 0);
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variable reg_mode_bmr : std_logic;
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variable reg_mode_bmw : std_logic;
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variable reg_mode_bir : std_logic;
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variable reg_mode_biw : std_logic;
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variable reg_mode_bx : std_logic;
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variable reg_mode_wmr : std_logic;
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variable reg_mode_wmw : std_logic;
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variable reg_mode_wir : std_logic;
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variable reg_mode_wiw : std_logic;
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variable reg_mode_wx : std_logic;
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variable reg_mode_all : std_logic_vector(9 downto 0);
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variable bactive : std_logic;
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variable wactive : std_logic;
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variable status : std_logic_vector(3 downto 0);
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variable trigval : std_logic;
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begin
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bactive := '0';
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wactive := '0';
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status := (others => '0');
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if (brkpt_enable = '1') then
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for i in 0 to num_comparators - 1 loop
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reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width);
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reg_mask := brkpt_reg(i * reg_width + 31 downto i * reg_width + 16);
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reg_mode_bmr := brkpt_reg(i * reg_width + 32);
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reg_mode_wmr := brkpt_reg(i * reg_width + 33);
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reg_mode_bmw := brkpt_reg(i * reg_width + 34);
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reg_mode_wmw := brkpt_reg(i * reg_width + 35);
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reg_mode_bir := brkpt_reg(i * reg_width + 36);
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reg_mode_wir := brkpt_reg(i * reg_width + 37);
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reg_mode_biw := brkpt_reg(i * reg_width + 38);
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reg_mode_wiw := brkpt_reg(i * reg_width + 39);
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reg_mode_bx := brkpt_reg(i * reg_width + 40);
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reg_mode_wx := brkpt_reg(i * reg_width + 41);
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reg_mode_all := brkpt_reg(i * reg_width + 41 downto i * reg_width + 32);
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trigval := brkpt_reg(i * reg_width + 42 + to_integer(unsigned(trig)));
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if (trigval = '1' and ((Addr and reg_mask) = reg_addr or (reg_mode_all = "0000000000"))) then
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if (Sync = '1') then
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if (reg_mode_bx = '1') then
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bactive := '1';
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status := "1000";
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elsif (reg_mode_wx = '1') then
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wactive := '1';
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status := "1001";
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end if;
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elsif (Rd_n = '0') then
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if (reg_mode_bmr = '1') then
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bactive := '1';
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status := "0000";
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elsif (reg_mode_wmr = '1') then
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wactive := '1';
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status := "0001";
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end if;
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elsif (Wr_n = '0') then
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if (reg_mode_bmw = '1') then
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bactive := '1';
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status := "0010";
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elsif (reg_mode_wmw = '1') then
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wactive := '1';
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status := "0011";
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end if;
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elsif (RdIO_n = '0') then
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if (reg_mode_bir = '1') then
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bactive := '1';
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status := "0100";
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elsif (reg_mode_wir = '1') then
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wactive := '1';
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status := "0101";
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end if;
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elsif (WrIO_n = '0') then
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if (reg_mode_biw = '1') then
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bactive := '1';
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status := "0110";
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elsif (reg_mode_wiw = '1') then
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wactive := '1';
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status := "0111";
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end if;
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end if;
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end if;
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end loop;
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end if;
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watch_active <= wactive;
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brkpt_active <= bactive;
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bw_status <= status;
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end process;
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-- CPU Control Commands
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-- 00000x Enable/Disable single stepping
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-- 00001x Enable/Disable breakpoints / watches
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-- 00010x Load breakpoint / watch register
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-- 00011x Reset CPU
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-- 001000 Singe Step CPU
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-- 001001 Read FIFO
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-- 001010 Reset FIFO
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-- 001011 Unused
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-- 00110x Load address/data register
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-- 00111x Unused
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-- 010000 Read Memory
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-- 010001 Read Memory and Auto Inc Address
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-- 010010 Write Memory
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-- 010011 Write Memory and Auto Inc Address
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-- 010100 Read IO
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-- 010101 Read IO and Auto Inc Address
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-- 010110 Write IO
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-- 010111 Write IO and Auto Inc Address
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-- 011000 Execute 6502 instruction
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-- 0111xx Unused
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-- 011x1x Unused
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-- 011xx1 Unused
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-- 10xxxx Int Ctrl
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-- 1100xx Timer Mode
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-- 00 - count cpu cycles where clken = 1 and CountCycle = 1
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-- 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
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-- 10 - free running timer, using busmon_clk as the source
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-- 11 - free running timer, using trig0 as the source
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-- Use trig0 to drive a free running counter for absolute timings
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ext_clk <= trig(0);
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timer1Process: process (ext_clk)
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begin
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if rising_edge(ext_clk) then
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timer1Count <= timer1Count + 1;
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end if;
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end process;
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cpuProcess: process (busmon_clk)
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begin
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if rising_edge(busmon_clk) then
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timer0Count <= timer0Count + 1;
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if busmon_clken = '1' then
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-- Cycle counter
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if (cpu_reset_n = '0') then
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cycleCount <= (others => '0');
|
|
elsif (CountCycle = '1' or timer_mode(0) = '1') then
|
|
cycleCount <= cycleCount + 1;
|
|
end if;
|
|
-- Command processing
|
|
cmd_edge1 <= cmd_edge;
|
|
cmd_edge2 <= cmd_edge1;
|
|
fifo_rd <= '0';
|
|
fifo_wr <= '0';
|
|
fifo_rst <= '0';
|
|
memory_rd <= '0';
|
|
memory_wr <= '0';
|
|
io_rd <= '0';
|
|
io_wr <= '0';
|
|
exec <= '0';
|
|
SS_Step <= '0';
|
|
if (cmd_edge2 /= cmd_edge1) then
|
|
if (cmd(5 downto 1) = "00000") then
|
|
single <= cmd(0);
|
|
end if;
|
|
|
|
if (cmd(5 downto 1) = "00001") then
|
|
brkpt_enable <= cmd(0);
|
|
end if;
|
|
|
|
if (cmd(5 downto 1) = "00010") then
|
|
brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
|
|
end if;
|
|
|
|
if (cmd(5 downto 1) = "00110") then
|
|
addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
|
|
end if;
|
|
|
|
if (cmd(5 downto 1) = "00011") then
|
|
reset <= cmd(0);
|
|
end if;
|
|
|
|
if (cmd(5 downto 0) = "01001") then
|
|
fifo_rd <= '1';
|
|
end if;
|
|
|
|
if (cmd(5 downto 0) = "01010") then
|
|
fifo_rst <= '1';
|
|
end if;
|
|
|
|
if (cmd(5 downto 1) = "01000") then
|
|
memory_rd <= '1';
|
|
auto_inc <= cmd(0);
|
|
end if;
|
|
|
|
if (cmd(5 downto 1) = "01001") then
|
|
memory_wr <= '1';
|
|
auto_inc <= cmd(0);
|
|
end if;
|
|
|
|
if (cmd(5 downto 1) = "01010") then
|
|
io_rd <= '1';
|
|
auto_inc <= cmd(0);
|
|
end if;
|
|
|
|
if (cmd(5 downto 1) = "01011") then
|
|
io_wr <= '1';
|
|
auto_inc <= cmd(0);
|
|
end if;
|
|
|
|
if (cmd(5 downto 0) = "011000") then
|
|
exec <= '1';
|
|
end if;
|
|
|
|
if (cmd(5 downto 4) = "10") then
|
|
int_ctrl(to_integer(unsigned(cmd(3 downto 2))) * 2 + 1 downto to_integer(unsigned(cmd(3 downto 2))) * 2) <= cmd(1 downto 0);
|
|
end if;
|
|
|
|
if (cmd(5 downto 2) = "1100") then
|
|
timer_mode <= cmd(1 downto 0);
|
|
end if;
|
|
|
|
-- Acknowlege certain commands immediately
|
|
if cmd(5 downto 4) /= "01" then
|
|
cmd_ack <= not cmd_ack;
|
|
end if;
|
|
|
|
end if;
|
|
|
|
if cmd_done = '1' then
|
|
-- Acknowlege memory access commands when thet complete
|
|
cmd_ack <= not cmd_ack;
|
|
-- Auto increment the memory address reg the cycle after a rd/wr
|
|
if auto_inc = '1' then
|
|
addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1;
|
|
end if;
|
|
end if;
|
|
|
|
-- Single Stepping
|
|
if (brkpt_active = '1') then
|
|
single <= '1';
|
|
end if;
|
|
|
|
if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
|
|
Rdy_int <= (not brkpt_active);
|
|
SS_Step <= (not brkpt_active);
|
|
else
|
|
Rdy_int <= (not Sync);
|
|
end if;
|
|
|
|
-- Latch instruction address for the whole cycle
|
|
if (Sync = '1') then
|
|
addr_inst <= Addr;
|
|
if timer_mode = "10" then
|
|
instrCount <= timer0Count;
|
|
elsif timer_mode = "11" then
|
|
instrCount <= timer1Count;
|
|
else
|
|
instrCount <= cycleCount;
|
|
end if;
|
|
end if;
|
|
|
|
-- Breakpoints and Watches written to the FIFO
|
|
brkpt_active1 <= brkpt_active;
|
|
bw_status1 <= bw_status;
|
|
if watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') then
|
|
fifo_wr <= '1';
|
|
Addr1 <= Addr;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
dataProcess: process (cpu_clk)
|
|
begin
|
|
if rising_edge(cpu_clk) then
|
|
if cpu_clken = '1' then
|
|
-- Latch the data bus for use in watches
|
|
Data1 <= Data;
|
|
-- Latch memory read in response to a read command
|
|
if (Done = '1') then
|
|
din_reg <= DataIn;
|
|
end if;
|
|
-- Delay the increnting of the address by one cycle
|
|
last_done <= Done;
|
|
if Done = '1' and last_done = '0' then
|
|
cmd_done <= '1';
|
|
else
|
|
cmd_done <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
Rdy <= Rdy_int;
|
|
RdMemOut <= memory_rd;
|
|
WrMemOut <= memory_wr;
|
|
RdIOOut <= io_rd;
|
|
WrIOOut <= io_wr;
|
|
AddrOut <= addr_dout_reg(23 downto 8);
|
|
DataOut <= addr_dout_reg(7 downto 0);
|
|
SS_Single <= single;
|
|
ExecOut <= exec;
|
|
|
|
-- Reset Logic
|
|
-- Generate a short (~1ms @ 1MHz) power up reset pulse
|
|
--
|
|
-- This is in case FPGA configuration takes longer than
|
|
-- the length of the host system reset pulse.
|
|
--
|
|
-- Some 6502 cores (particularly the AlanD core) needs
|
|
-- reset to be asserted to start.
|
|
|
|
|
|
|
|
-- Debounce nRSTin using clock_avr as this is always 16MHz
|
|
-- nrst1 is the possibly glitchy input
|
|
-- nrst2 is the filtered output
|
|
process(clock_avr)
|
|
begin
|
|
if rising_edge(clock_avr) then
|
|
-- Syncronise nRSTin
|
|
nrst1 <= nRSTin and (not sw_reset_cpu);
|
|
-- De-glitch NRST
|
|
if nrst1 = '0' then
|
|
nrst_counter <= to_unsigned(0, nrst_counter'length);
|
|
nrst2 <= '0';
|
|
elsif nrst_counter(nrst_counter'high) = '0' then
|
|
nrst_counter <= nrst_counter + 1;
|
|
else
|
|
nrst2 <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
process(cpu_clk)
|
|
begin
|
|
if rising_edge(cpu_clk) then
|
|
if cpu_clken = '1' then
|
|
if reset_counter(reset_counter'high) = '0' then
|
|
reset_counter <= reset_counter + 1;
|
|
end if;
|
|
nrst3 <= nrst2 and reset_counter(reset_counter'high) and (not reset);
|
|
cpu_reset_n <= nrst3;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
nRSTout <= cpu_reset_n;
|
|
|
|
end behavioral;
|