mirror of
https://github.com/hoglet67/AtomBusMon.git
synced 2025-01-06 20:35:36 +00:00
279 lines
9.3 KiB
VHDL
279 lines
9.3 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : AtomBusMon.vhd
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-- /___/ /\ Timestamp : 30/05/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: AtomBusMon
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--Device: XC3S250E
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.OhoPack.all ;
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entity MOS6502CpuMonCore is
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generic (
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UseT65Core : boolean;
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UseAlanDCore : boolean;
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avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
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avr_prog_mem_size : integer := 1024 * 8 -- 6502 fits in 8K, others need 9K
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);
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port (
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clock_avr : in std_logic;
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busmon_clk : in std_logic;
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busmon_clken : in std_logic;
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cpu_clk : in std_logic;
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cpu_clken : in std_logic;
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-- 6502 Signals
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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Sync : out std_logic;
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Addr : out std_logic_vector(15 downto 0);
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R_W_n : out std_logic;
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Din : in std_logic_vector(7 downto 0);
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Dout : out std_logic_vector(7 downto 0);
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SO_n : in std_logic;
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Res_n_in : in std_logic;
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Res_n_out : out std_logic;
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Rdy : in std_logic;
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-- External trigger inputs
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trig : in std_logic_vector(1 downto 0);
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-- Serial Console
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avr_RxD : in std_logic;
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avr_TxD : out std_logic;
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-- GODIL Switches
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sw1 : in std_logic;
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nsw2 : in std_logic;
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-- GODIL LEDs
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led3 : out std_logic;
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led6 : out std_logic;
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led8 : out std_logic;
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-- OHO_DY1 connected to test connector
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tmosi : out std_logic;
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tdin : out std_logic;
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tcclk : out std_logic
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);
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end MOS6502CpuMonCore;
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architecture behavioral of MOS6502CpuMonCore is
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signal cpu_clken_ss : std_logic;
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signal Data : std_logic_vector(7 downto 0);
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signal Dout_int : std_logic_vector(7 downto 0);
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signal R_W_n_int : std_logic;
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signal Rd_n_int : std_logic;
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signal Wr_n_int : std_logic;
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signal Sync_int : std_logic;
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signal hold : std_logic;
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signal Addr_int : std_logic_vector(23 downto 0);
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signal IRQ_n_sync : std_logic;
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signal NMI_n_sync : std_logic;
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signal cpu_addr_us: unsigned (15 downto 0);
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signal cpu_dout_us: unsigned (7 downto 0);
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signal Regs : std_logic_vector(63 downto 0);
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signal Regs1 : std_logic_vector(255 downto 0);
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signal last_PC : std_logic_vector(15 downto 0);
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signal SS_Single : std_logic;
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signal SS_Step : std_logic;
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signal CountCycle : std_logic;
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signal memory_rd : std_logic;
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signal memory_rd1 : std_logic;
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signal memory_wr : std_logic;
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signal memory_wr1 : std_logic;
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signal memory_addr : std_logic_vector(15 downto 0);
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signal memory_addr1 : std_logic_vector(15 downto 0);
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signal memory_dout : std_logic_vector(7 downto 0);
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signal memory_din : std_logic_vector(7 downto 0);
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signal memory_done : std_logic;
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begin
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mon : entity work.BusMonCore
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generic map (
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avr_data_mem_size => avr_data_mem_size,
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avr_prog_mem_size => avr_prog_mem_size
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)
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port map (
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clock_avr => clock_avr,
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busmon_clk => busmon_clk,
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busmon_clken => busmon_clken,
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cpu_clk => cpu_clk,
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cpu_clken => cpu_clken,
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Addr => Addr_int(15 downto 0),
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Data => Data,
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Rd_n => Rd_n_int,
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Wr_n => Wr_n_int,
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RdIO_n => '1',
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WrIO_n => '1',
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Sync => Sync_int,
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Rdy => open,
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nRSTin => Res_n_in,
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nRSTout => Res_n_out,
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CountCycle => CountCycle,
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trig => trig,
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lcd_rs => open,
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lcd_rw => open,
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lcd_e => open,
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lcd_db => open,
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avr_RxD => avr_RxD,
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avr_TxD => avr_TxD,
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sw1 => sw1,
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nsw2 => nsw2,
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led3 => led3,
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led6 => led6,
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led8 => led8,
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tmosi => tmosi,
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tdin => tdin,
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tcclk => tcclk,
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Regs => Regs1,
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RdMemOut => memory_rd,
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WrMemOut => memory_wr,
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RdIOOut => open,
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WrIOOut => open,
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AddrOut => memory_addr,
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DataOut => memory_dout,
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DataIn => memory_din,
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Done => memory_done,
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SS_Step => SS_Step,
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SS_Single => SS_Single
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);
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Wr_n_int <= R_W_n_int;
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Rd_n_int <= not R_W_n_int;
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Data <= Din when R_W_n_int = '1' else Dout_int;
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-- The CPU is slightly pipelined and the register update of the last
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-- instruction overlaps with the opcode fetch of the next instruction.
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--
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-- If the single stepping stopped on the opcode fetch cycle, then the registers
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-- valued would not accurately reflect the previous instruction.
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--
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-- To work around this, when single stepping, we stop on the cycle after
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-- the opcode fetch, which means the program counter has advanced.
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--
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-- To hide this from the user single stepping, all we need to do is to
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-- also pipeline the value of the program counter by one stage to compensate.
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last_pc_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (cpu_clken = '1') then
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if (hold = '0') then
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last_PC <= Regs(63 downto 48);
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end if;
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end if;
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end if;
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end process;
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Regs1( 47 downto 0) <= Regs( 47 downto 0);
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Regs1( 63 downto 48) <= last_PC;
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Regs1(255 downto 64) <= (others => '0');
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cpu_clken_ss <= (not hold) and cpu_clken;
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GenT65Core: if UseT65Core generate
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inst_t65: entity work.T65 port map (
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mode => "00",
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Abort_n => '1',
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SO_n => SO_n,
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Res_n => Res_n_in,
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Enable => cpu_clken_ss,
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Clk => cpu_clk,
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Rdy => '1',
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IRQ_n => IRQ_n,
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NMI_n => NMI_n,
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R_W_n => R_W_n_int,
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Sync => Sync_int,
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A => Addr_int,
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DI => Din,
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DO => Dout_int,
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Regs => Regs
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);
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end generate;
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GenAlanDCore: if UseAlanDCore generate
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inst_r65c02: entity work.r65c02 port map (
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reset => Res_n_in,
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clk => cpu_clk,
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enable => cpu_clken_ss,
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nmi_n => NMI_n,
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irq_n => IRQ_n,
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di => unsigned(Din),
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do => cpu_dout_us,
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addr => cpu_addr_us,
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nwe => R_W_n_int,
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sync => Sync_int,
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sync_irq => open,
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Regs => Regs
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);
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Dout_int <= std_logic_vector(cpu_dout_us);
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Addr_int(15 downto 0) <= std_logic_vector(cpu_addr_us);
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end generate;
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-- This block generates a hold signal that acts as the inverse of a clock enable
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-- for the CPU. See comments above for why this is a cycle delayed a cycle.
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hold_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (cpu_clken = '1') then
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if (Sync_int = '1') then
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-- stop after the opcode has been fetched
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hold <= SS_Single;
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elsif (SS_Step = '1') then
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-- start again when the single step command is issues
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hold <= '0';
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end if;
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end if;
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end if;
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end process;
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-- Only count cycles when the 6809 is actually running
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CountCycle <= not hold;
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-- this block delays memory_rd, memory_wr, memory_addr until the start of the next cpu clk cycle
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-- necessary because the cpu mon block is clocked of the opposite edge of the clock
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-- this allows a full cpu clk cycle for cpu mon reads and writes
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mem_gen : process(cpu_clk)
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begin
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if rising_edge(cpu_clk) then
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if (cpu_clken = '1') then
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memory_rd1 <= memory_rd;
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memory_wr1 <= memory_wr;
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memory_addr1 <= memory_addr;
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end if;
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end if;
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end process;
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R_W_n <= '1' when memory_rd1 = '1' else '0' when memory_wr1 = '1' else R_W_n_int;
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Addr <= memory_addr1 when (memory_rd1 = '1' or memory_wr1 = '1') else Addr_int(15 downto 0);
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Sync <= Sync_int;
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Dout <= memory_dout when memory_wr1 = '1' else Dout_int;
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memory_done <= memory_rd1 or memory_wr1;
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memory_din <= Din;
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end behavioral;
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