2024-03-16 19:00:23 +00:00
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//
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// I2C.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/03/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#include "I2C.hpp"
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2024-03-18 15:09:29 +00:00
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#include "../../Outputs/Log.hpp"
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2024-03-16 19:00:23 +00:00
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using namespace I2C;
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2024-03-18 15:09:29 +00:00
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namespace {
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Log::Logger<Log::Source::I2C> logger;
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}
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2024-11-30 22:21:00 +00:00
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void Bus::set_data(const bool pulled) {
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2024-03-16 19:00:23 +00:00
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set_clock_data(clock_, pulled);
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}
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2024-11-30 22:21:00 +00:00
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bool Bus::data() const {
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2024-03-18 01:55:19 +00:00
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bool result = data_;
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if(peripheral_bits_) {
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2024-03-27 01:33:46 +00:00
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result |= !(peripheral_response_ & 0x80);
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2024-03-18 01:55:19 +00:00
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}
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return result;
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2024-03-16 19:00:23 +00:00
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}
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2024-11-30 22:21:00 +00:00
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void Bus::set_clock(const bool pulled) {
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2024-03-16 19:00:23 +00:00
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set_clock_data(pulled, data_);
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}
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2024-11-30 22:21:00 +00:00
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bool Bus::clock() const {
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2024-03-16 19:00:23 +00:00
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return clock_;
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}
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2024-11-30 22:21:00 +00:00
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void Bus::set_clock_data(const bool clock_pulled, const bool data_pulled) {
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// Proceed only if changes are evidenced.
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2024-03-26 02:10:52 +00:00
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if(clock_pulled == clock_ && data_pulled == data_) {
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return;
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}
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2024-03-27 01:33:46 +00:00
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const bool prior_clock = clock_;
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const bool prior_data = data_;
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2024-03-16 19:00:23 +00:00
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clock_ = clock_pulled;
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data_ = data_pulled;
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2024-03-17 02:02:16 +00:00
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2024-03-27 01:52:29 +00:00
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// If currently serialising from a peripheral then shift onwards on
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// every clock trailing edge.
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2024-03-27 01:33:46 +00:00
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if(peripheral_bits_) {
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// Trailing edge of clock => bit has been consumed.
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if(!prior_clock && clock_) {
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logger.info().append("<< %d", (peripheral_response_ >> 7) & 1);
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--peripheral_bits_;
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peripheral_response_ <<= 1;
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if(!peripheral_bits_) {
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signal(Event::FinishedOutput);
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}
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}
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2024-03-26 02:10:52 +00:00
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return;
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}
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2024-03-18 15:09:29 +00:00
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2024-03-27 01:52:29 +00:00
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// Not currently serialising implies listening.
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if(!clock_ && prior_data != data_) {
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2024-03-27 01:52:29 +00:00
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// A data transition outside of a clock cycle implies a start or stop.
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in_bit_ = false;
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if(data_) {
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2024-03-27 01:33:46 +00:00
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logger.info().append("S");
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2024-03-26 02:10:52 +00:00
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signal(Event::Start);
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} else {
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logger.info().append("W");
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2024-03-26 02:10:52 +00:00
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signal(Event::Stop);
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}
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2024-03-27 01:33:46 +00:00
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} else if(clock_ != prior_clock) {
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// Bits: wait until the falling edge of the cycle.
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if(!clock_) {
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// Rising edge: clock period begins.
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in_bit_ = true;
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} else if(in_bit_) {
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2024-03-27 01:52:29 +00:00
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// Falling edge: clock period ends (assuming it began; otherwise this is a preparatory
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// clock transition only, immediately after a start bit).
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2024-03-27 01:33:46 +00:00
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in_bit_ = false;
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if(data_) {
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logger.info().append("0");
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signal(Event::Zero);
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} else {
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logger.info().append("1");
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signal(Event::One);
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}
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2024-03-26 02:10:52 +00:00
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}
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2024-03-18 01:55:19 +00:00
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}
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2024-03-26 02:10:52 +00:00
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}
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2024-03-17 02:02:16 +00:00
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2024-11-30 22:21:00 +00:00
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void Bus::signal(const Event event) {
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const auto capture_bit = [&]() {
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input_ = uint16_t((input_ << 1) | (event == Event::Zero ? 0 : 1));
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++input_count_;
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};
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const auto acknowledge = [&]() {
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// Post an acknowledgement bit.
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peripheral_response_ = 0;
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peripheral_bits_ = 1;
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};
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const auto set_state = [&](State state) {
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state_ = state;
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input_count_ = 0;
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input_ = 0;
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};
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const auto enqueue = [&](std::optional<uint8_t> next) {
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if(next) {
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peripheral_response_ = static_cast<uint16_t>(*next);
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peripheral_bits_ = 8;
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set_state(State::AwaitingByteAcknowledge);
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2024-03-26 16:24:24 +00:00
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} else {
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set_state(State::AwaitingAddress);
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}
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};
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2024-03-27 01:52:29 +00:00
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const auto stop = [&]() {
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set_state(State::AwaitingAddress);
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active_peripheral_ = nullptr;
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};
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2024-03-26 16:24:24 +00:00
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// Allow start and stop conditions at any time.
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if(event == Event::Start) {
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set_state(State::CollectingAddress);
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active_peripheral_ = nullptr;
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return;
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}
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2024-03-26 02:10:52 +00:00
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if(event == Event::Stop) {
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2024-03-26 16:24:24 +00:00
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if(active_peripheral_) {
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active_peripheral_->stop();
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}
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2024-03-27 01:52:29 +00:00
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stop();
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2024-03-26 16:24:24 +00:00
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return;
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2024-03-18 01:55:19 +00:00
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}
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2024-03-26 16:24:24 +00:00
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switch(state_) {
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2024-03-27 01:52:29 +00:00
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// While waiting for an address, don't respond to anything other than a
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// start bit, which is actually dealt with above.
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2024-03-26 16:24:24 +00:00
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case State::AwaitingAddress: break;
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2024-03-18 01:55:19 +00:00
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2024-03-27 01:52:29 +00:00
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// To collect an address: shift in eight bits, and if there's a device
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// at that address then acknowledge the address and segue into a read
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// or write loop.
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2024-03-26 16:24:24 +00:00
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case State::CollectingAddress:
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2024-03-18 01:55:19 +00:00
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capture_bit();
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2024-03-26 16:24:24 +00:00
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if(input_count_ == 8) {
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2024-03-18 15:09:29 +00:00
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auto pair = peripherals_.find(uint8_t(input_) & 0xfe);
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2024-03-18 01:55:19 +00:00
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if(pair != peripherals_.end()) {
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active_peripheral_ = pair->second;
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2024-03-26 16:24:24 +00:00
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active_peripheral_->start(input_ & 1);
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if(input_&1) {
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2024-03-26 18:06:11 +00:00
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acknowledge();
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2024-03-27 01:52:29 +00:00
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set_state(State::CompletingReadAcknowledge);
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2024-03-26 16:24:24 +00:00
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} else {
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acknowledge();
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set_state(State::ReceivingByte);
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}
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2024-03-18 01:55:19 +00:00
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} else {
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2024-03-26 16:24:24 +00:00
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state_ = State::AwaitingAddress;
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2024-03-17 02:02:16 +00:00
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}
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2024-03-18 01:55:19 +00:00
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}
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break;
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2024-03-17 02:02:16 +00:00
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2024-03-27 01:52:29 +00:00
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// Receiving byte: wait until a scheduled acknowledgment has
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// happened, then collect eight bits, then see whether the
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// active peripheral will accept them. If so, acknowledge and repeat.
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// Otherwise fall silent.
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2024-03-26 16:24:24 +00:00
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case State::ReceivingByte:
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2024-03-27 01:33:46 +00:00
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if(event == Event::FinishedOutput) {
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return;
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2024-03-18 01:55:19 +00:00
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}
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capture_bit();
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if(input_count_ == 8) {
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2024-03-27 01:52:29 +00:00
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if(active_peripheral_->write(static_cast<uint8_t>(input_))) {
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acknowledge();
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set_state(State::ReceivingByte);
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} else {
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stop();
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}
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2024-03-26 16:24:24 +00:00
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}
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break;
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2024-03-18 15:09:29 +00:00
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2024-03-27 01:52:29 +00:00
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// The initial state immediately after a peripheral has been started
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// in read mode and the address-select acknowledgement is still
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// being serialised.
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//
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// Once that is completed, enqueues the first byte from the peripheral.
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case State::CompletingReadAcknowledge:
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2024-03-27 01:33:46 +00:00
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if(event != Event::FinishedOutput) {
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break;
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}
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enqueue(active_peripheral_->read());
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break;
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2024-03-27 01:52:29 +00:00
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// Repeating state during reading; waits until the previous byte has
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// been fully serialised, and if the host acknowledged it then posts
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// the next. If the host didn't acknowledge, stops the connection.
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2024-03-27 01:33:46 +00:00
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case State::AwaitingByteAcknowledge:
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if(event == Event::FinishedOutput) {
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break;
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}
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if(event != Event::Zero) {
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2024-03-27 01:52:29 +00:00
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stop();
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2024-03-27 01:33:46 +00:00
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break;
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2024-03-18 01:55:19 +00:00
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}
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2024-03-26 16:24:24 +00:00
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2024-03-27 01:33:46 +00:00
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// Add a new byte if there is one.
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2024-03-26 16:24:24 +00:00
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enqueue(active_peripheral_->read());
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2024-03-18 01:55:19 +00:00
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break;
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2024-03-17 02:02:16 +00:00
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}
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2024-03-16 19:00:23 +00:00
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}
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2024-11-30 22:21:00 +00:00
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void Bus::add_peripheral(Peripheral *const peripheral, const int address) {
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2024-03-16 19:00:23 +00:00
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peripherals_[address] = peripheral;
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}
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