2022-05-12 23:46:08 +00:00
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//
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// Instruction.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 12/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#include "Instruction.hpp"
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#include <cassert>
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using namespace InstructionSet::M68k;
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std::string Preinstruction::operand_description(int index, int opcode) const {
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switch(mode(index)) {
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default: assert(false);
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case AddressingMode::None:
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return "";
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case AddressingMode::DataRegisterDirect:
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return std::string("D") + std::to_string(reg(index));
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case AddressingMode::AddressRegisterDirect:
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return std::string("A") + std::to_string(reg(index));
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case AddressingMode::AddressRegisterIndirect:
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return std::string("(A") + std::to_string(reg(index)) + ")";
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case AddressingMode::AddressRegisterIndirectWithPostincrement:
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return std::string("(A") + std::to_string(reg(index)) + ")+";
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case AddressingMode::AddressRegisterIndirectWithPredecrement:
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return std::string("-(A") + std::to_string(reg(index)) + ")";
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case AddressingMode::AddressRegisterIndirectWithDisplacement:
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return std::string("(d16, A") + std::to_string(reg(index)) + ")";
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case AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement:
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return std::string("(d8, A") + std::to_string(reg(index)) + ", Xn)";
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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return "(d16, PC)";
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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return "(d8, PC, Xn)";
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case AddressingMode::AbsoluteShort:
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return "(xxx).w";
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case AddressingMode::AbsoluteLong:
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return "(xxx).l";
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case AddressingMode::ImmediateData:
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return "#";
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case AddressingMode::Quick:
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if(opcode == -1) {
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return "Q";
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}
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return std::to_string(int(quick(uint16_t(opcode), operation)));
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}
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}
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std::string Preinstruction::to_string(int opcode) const {
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bool flip_operands = false;
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const char *instruction;
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switch(operation) {
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2022-05-29 19:28:16 +00:00
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case Operation::Undefined: return "None";
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2022-05-12 23:46:08 +00:00
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case Operation::NOP: instruction = "NOP"; break;
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case Operation::ABCD: instruction = "ABCD"; break;
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case Operation::SBCD: instruction = "SBCD"; break;
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case Operation::NBCD: instruction = "NBCD"; break;
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case Operation::ADDb: instruction = "ADD.b"; break;
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case Operation::ADDw: instruction = "ADD.w"; break;
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case Operation::ADDl: instruction = "ADD.l"; break;
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case Operation::ADDAw:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "ADD.w";
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} else {
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instruction = "ADDA.w";
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}
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break;
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case Operation::ADDAl:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "ADD.l";
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} else {
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instruction = "ADDA.l";
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}
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break;
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case Operation::ADDXb: instruction = "ADDX.b"; break;
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case Operation::ADDXw: instruction = "ADDX.w"; break;
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case Operation::ADDXl: instruction = "ADDX.l"; break;
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case Operation::SUBb: instruction = "SUB.b"; break;
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case Operation::SUBw: instruction = "SUB.w"; break;
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case Operation::SUBl: instruction = "SUB.l"; break;
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case Operation::SUBAw:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "SUB.w";
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} else {
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instruction = "SUBA.w";
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}
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break;
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case Operation::SUBAl:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "SUB.l";
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} else {
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instruction = "SUBA.l";
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}
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break;
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case Operation::SUBXb: instruction = "SUBX.b"; break;
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case Operation::SUBXw: instruction = "SUBX.w"; break;
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case Operation::SUBXl: instruction = "SUBX.l"; break;
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case Operation::MOVEb: instruction = "MOVE.b"; break;
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case Operation::MOVEw: instruction = "MOVE.w"; break;
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case Operation::MOVEl:
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if(mode<0>() == AddressingMode::Quick) {
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instruction = "MOVE.q";
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} else {
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instruction = "MOVE.l";
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}
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break;
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case Operation::MOVEAw: instruction = "MOVEA.w"; break;
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case Operation::MOVEAl: instruction = "MOVEA.l"; break;
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case Operation::LEA: instruction = "LEA"; break;
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case Operation::PEA: instruction = "PEA"; break;
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case Operation::MOVEtoSR: instruction = "MOVEtoSR"; break;
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case Operation::MOVEfromSR: instruction = "MOVEfromSR"; break;
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case Operation::MOVEtoCCR: instruction = "MOVEtoCCR"; break;
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case Operation::MOVEtoUSP: instruction = "MOVEtoUSP"; break;
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case Operation::MOVEfromUSP: instruction = "MOVEfromUSP"; break;
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case Operation::ORItoSR: instruction = "ORItoSR"; break;
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case Operation::ORItoCCR: instruction = "ORItoCCR"; break;
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case Operation::ANDItoSR: instruction = "ANDItoSR"; break;
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case Operation::ANDItoCCR: instruction = "ANDItoCCR"; break;
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case Operation::EORItoSR: instruction = "EORItoSR"; break;
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case Operation::EORItoCCR: instruction = "EORItoCCR"; break;
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case Operation::BTST: instruction = "BTST"; break;
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case Operation::BCLR: instruction = "BCLR"; break;
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case Operation::BCHG: instruction = "BCHG"; break;
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case Operation::BSET: instruction = "BSET"; break;
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case Operation::CMPb: instruction = "CMP.b"; break;
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case Operation::CMPw: instruction = "CMP.w"; break;
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case Operation::CMPl: instruction = "CMP.l"; break;
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case Operation::CMPAw: instruction = "CMPA.w"; break;
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case Operation::CMPAl: instruction = "CMPA.l"; break;
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case Operation::TSTb: instruction = "TST.b"; break;
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case Operation::TSTw: instruction = "TST.w"; break;
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case Operation::TSTl: instruction = "TST.l"; break;
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case Operation::JMP: instruction = "JMP"; break;
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case Operation::JSR: instruction = "JSR"; break;
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case Operation::RTS: instruction = "RTS"; break;
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case Operation::DBcc: instruction = "DBcc"; break;
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case Operation::Scc: instruction = "Scc"; break;
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case Operation::Bccb:
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case Operation::Bccl:
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case Operation::Bccw: instruction = "Bcc"; break;
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case Operation::BSRb:
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case Operation::BSRl:
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case Operation::BSRw: instruction = "BSR"; break;
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case Operation::CLRb: instruction = "CLR.b"; break;
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case Operation::CLRw: instruction = "CLR.w"; break;
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case Operation::CLRl: instruction = "CLR.l"; break;
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case Operation::NEGXb: instruction = "NEGX.b"; break;
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case Operation::NEGXw: instruction = "NEGX.w"; break;
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case Operation::NEGXl: instruction = "NEGX.l"; break;
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case Operation::NEGb: instruction = "NEG.b"; break;
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case Operation::NEGw: instruction = "NEG.w"; break;
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case Operation::NEGl: instruction = "NEG.l"; break;
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case Operation::ASLb: instruction = "ASL.b"; break;
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case Operation::ASLw: instruction = "ASL.w"; break;
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case Operation::ASLl: instruction = "ASL.l"; break;
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case Operation::ASLm: instruction = "ASL.w"; break;
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case Operation::ASRb: instruction = "ASR.b"; break;
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case Operation::ASRw: instruction = "ASR.w"; break;
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case Operation::ASRl: instruction = "ASR.l"; break;
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case Operation::ASRm: instruction = "ASR.w"; break;
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case Operation::LSLb: instruction = "LSL.b"; break;
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case Operation::LSLw: instruction = "LSL.w"; break;
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case Operation::LSLl: instruction = "LSL.l"; break;
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case Operation::LSLm: instruction = "LSL.w"; break;
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case Operation::LSRb: instruction = "LSR.b"; break;
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case Operation::LSRw: instruction = "LSR.w"; break;
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case Operation::LSRl: instruction = "LSR.l"; break;
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case Operation::LSRm: instruction = "LSR.w"; break;
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case Operation::ROLb: instruction = "ROL.b"; break;
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case Operation::ROLw: instruction = "ROL.w"; break;
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case Operation::ROLl: instruction = "ROL.l"; break;
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case Operation::ROLm: instruction = "ROL.w"; break;
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case Operation::RORb: instruction = "ROR.b"; break;
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case Operation::RORw: instruction = "ROR.w"; break;
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case Operation::RORl: instruction = "ROR.l"; break;
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case Operation::RORm: instruction = "ROR.w"; break;
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case Operation::ROXLb: instruction = "ROXL.b"; break;
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case Operation::ROXLw: instruction = "ROXL.w"; break;
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case Operation::ROXLl: instruction = "ROXL.l"; break;
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case Operation::ROXLm: instruction = "ROXL.w"; break;
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case Operation::ROXRb: instruction = "ROXR.b"; break;
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case Operation::ROXRw: instruction = "ROXR.w"; break;
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case Operation::ROXRl: instruction = "ROXR.l"; break;
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case Operation::ROXRm: instruction = "ROXR.w"; break;
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case Operation::MOVEMtoMl: instruction = "MOVEM.l"; break;
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case Operation::MOVEMtoMw: instruction = "MOVEM.w"; break;
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case Operation::MOVEMtoRl:
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instruction = "MOVEM.l";
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flip_operands = true;
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break;
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case Operation::MOVEMtoRw:
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instruction = "MOVEM.w";
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flip_operands = true;
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break;
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case Operation::MOVEPl: instruction = "MOVEP.l"; break;
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case Operation::MOVEPw: instruction = "MOVEP.w"; break;
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case Operation::ANDb: instruction = "AND.b"; break;
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case Operation::ANDw: instruction = "AND.w"; break;
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case Operation::ANDl: instruction = "AND.l"; break;
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case Operation::EORb: instruction = "EOR.b"; break;
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case Operation::EORw: instruction = "EOR.w"; break;
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case Operation::EORl: instruction = "EOR.l"; break;
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case Operation::NOTb: instruction = "NOT.b"; break;
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case Operation::NOTw: instruction = "NOT.w"; break;
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case Operation::NOTl: instruction = "NOT.l"; break;
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case Operation::ORb: instruction = "OR.b"; break;
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case Operation::ORw: instruction = "OR.w"; break;
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case Operation::ORl: instruction = "OR.l"; break;
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case Operation::MULU: instruction = "MULU"; break;
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case Operation::MULS: instruction = "MULS"; break;
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case Operation::DIVU: instruction = "DIVU"; break;
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case Operation::DIVS: instruction = "DIVS"; break;
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case Operation::RTE: instruction = "RTE"; break;
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case Operation::RTR: instruction = "RTR"; break;
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case Operation::TRAP: instruction = "TRAP"; break;
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case Operation::TRAPV: instruction = "TRAPV"; break;
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case Operation::CHK: instruction = "CHK"; break;
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case Operation::EXG: instruction = "EXG"; break;
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case Operation::SWAP: instruction = "SWAP"; break;
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case Operation::TAS: instruction = "TAS"; break;
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case Operation::EXTbtow: instruction = "EXT.w"; break;
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case Operation::EXTwtol: instruction = "EXT.l"; break;
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case Operation::LINKw: instruction = "LINK"; break;
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case Operation::UNLINK: instruction = "UNLINK"; break;
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case Operation::STOP: instruction = "STOP"; break;
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case Operation::RESET: instruction = "RESET"; break;
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default:
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assert(false);
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}
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const std::string operand1 = operand_description(0 ^ int(flip_operands), opcode);
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const std::string operand2 = operand_description(1 ^ int(flip_operands), opcode);
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std::string result = instruction;
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if(!operand1.empty()) result += std::string(" ") + operand1;
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if(!operand2.empty()) result += std::string(", ") + operand2;
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return result;
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}
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