2020-10-26 01:31:21 +00:00
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//
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// IIgsMemoryMapTests.mm
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// Clock SignalTests
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//
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// Created by Thomas Harte on 25/10/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include "../../../Machines/Apple/AppleIIgs/MemoryMap.hpp"
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2020-10-26 01:40:50 +00:00
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namespace {
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using MemoryMap = Apple::IIgs::MemoryMap;
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}
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2020-10-26 01:31:21 +00:00
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@interface IIgsMemoryMapTests : XCTestCase
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@end
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@implementation IIgsMemoryMapTests {
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2020-10-26 01:40:50 +00:00
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MemoryMap _memoryMap;
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2020-10-26 01:31:21 +00:00
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std::vector<uint8_t> _ram;
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std::vector<uint8_t> _rom;
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}
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- (void)setUp {
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_ram.resize((128 + 8 * 1024) * 1024);
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_rom.resize(256 * 1024);
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_memoryMap.set_storage(_ram, _rom);
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2020-12-07 03:01:59 +00:00
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// If this isn't the first test run, RAM and ROM may have old values.
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// Initialise to a known state.
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memset(_ram.data(), 0, _ram.size());
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memset(_rom.data(), 0, _rom.size());
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2020-10-26 01:31:21 +00:00
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}
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2020-10-27 23:59:41 +00:00
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- (void)write:(uint8_t)value address:(uint32_t)address {
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const auto ®ion = MemoryMapRegion(_memoryMap, address);
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2020-12-07 02:46:04 +00:00
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XCTAssertFalse(region.flags & MemoryMap::Region::IsIO);
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2020-10-27 23:59:41 +00:00
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MemoryMapWrite(_memoryMap, region, address, &value);
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}
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- (uint8_t)readAddress:(uint32_t)address {
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const auto ®ion = MemoryMapRegion(_memoryMap, address);
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uint8_t value;
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MemoryMapRead(region, address, &value);
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return value;
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}
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2020-12-07 02:53:53 +00:00
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- (void)testAllRAM {
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// Disable IO/LC 'shadowing', to give linear memory up to bank $80.
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_memoryMap.set_shadow_register(0x5f);
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2020-10-26 01:40:50 +00:00
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// Fill memory via the map.
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2020-12-07 02:53:53 +00:00
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for(int address = 0x00'0000; address < 0x80'0000; ++address) {
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const uint8_t value = uint8_t(address ^ (address >> 8) ^ (address >> 16));
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2020-10-27 23:59:41 +00:00
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[self write:value address:address];
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2020-10-26 01:40:50 +00:00
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}
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// Test by direct access.
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2020-12-07 02:53:53 +00:00
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for(int address = 0x00'0000; address < 0x80'0000; ++address) {
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const uint8_t value = uint8_t(address ^ (address >> 8) ^ (address >> 16));
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2020-10-27 23:59:41 +00:00
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XCTAssertEqual([self readAddress:address], value);
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2020-10-26 01:40:50 +00:00
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}
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2020-10-26 01:31:21 +00:00
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}
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2020-10-27 23:59:41 +00:00
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- (void)testROMIsReadonly {
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2020-10-26 01:40:50 +00:00
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_rom[0] = 0xc0;
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// Test that ROM can be read in the correct location.
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2020-12-07 02:19:38 +00:00
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XCTAssertEqual([self readAddress:0xfc'0000], 0xc0);
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2020-10-26 01:40:50 +00:00
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// Try writing to it, and check that nothing happened.
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2020-12-07 02:19:38 +00:00
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[self write:0xfc address:0xfc'0000];
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2020-10-26 01:40:50 +00:00
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XCTAssertEqual(_rom[0], 0xc0);
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2020-10-26 01:31:21 +00:00
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}
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2020-12-07 02:19:38 +00:00
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/// Tests that the same portion of ROM is visible in banks $00, $01, $e0 and $e1.
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- (void)testROMVisibility {
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2020-10-26 02:13:54 +00:00
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_rom.back() = 0xa8;
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2020-10-27 23:02:15 +00:00
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auto test_bank = [self](uint32_t bank) {
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2020-12-07 02:19:38 +00:00
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const uint32_t address = bank | 0xffff;
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2020-10-27 23:59:41 +00:00
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XCTAssertEqual([self readAddress:address], 0xa8);
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2020-10-27 23:02:15 +00:00
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};
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2020-10-26 02:13:54 +00:00
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2020-12-07 02:19:38 +00:00
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test_bank(0x00'0000);
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test_bank(0x01'0000);
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test_bank(0xe0'0000);
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test_bank(0xe1'0000);
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2020-10-26 02:13:54 +00:00
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}
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2020-12-07 02:19:38 +00:00
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/// Tests that writes to $00:$0400 and to $01:$0400 are subsequently visible at $e0:$0400 and $e1:$0400.
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2020-10-27 23:59:41 +00:00
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- (void)testShadowing {
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2020-12-07 02:19:38 +00:00
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[self write:0xab address:0x00'0400];
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[self write:0xcd address:0x01'0400];
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XCTAssertEqual([self readAddress:0xe0'0400], 0xab);
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XCTAssertEqual([self readAddress:0xe1'0400], 0xcd);
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}
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/// Tests that a write to bank $00 which via the auxiliary switches is redirected to bank $01 is then
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/// mirrored to $e1.
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- (void)testAuxiliaryShadowing {
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// Select the alternate text page 1.
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_memoryMap.access(0xc001, false); // Set 80STORE.
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_memoryMap.access(0xc055, false); // Set PAGE2.
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// These two things together should enable auxiliary memory for text page 1.
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// No, really.
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// Enable shadowing of text page 1.
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_memoryMap.set_shadow_register(0x00);
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// Establish a different value in bank $e1, then write
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2020-12-07 02:46:04 +00:00
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// to bank $00 and check banks $01 and $e1.
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2020-12-07 02:19:38 +00:00
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[self write: 0xcb address:0xe1'0400];
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[self write: 0xde address:0x00'0400];
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XCTAssertEqual([self readAddress:0xe1'0400], 0xde);
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2020-12-07 02:46:04 +00:00
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XCTAssertEqual([self readAddress:0x01'0400], 0xde);
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// Reset the $e1 page version and check all three detinations.
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[self write: 0xcb address:0xe1'0400];
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XCTAssertEqual([self readAddress:0xe1'0400], 0xcb);
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XCTAssertEqual([self readAddress:0x00'0400], 0xde);
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XCTAssertEqual([self readAddress:0x01'0400], 0xde);
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2020-10-27 23:59:41 +00:00
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}
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2020-12-11 02:48:04 +00:00
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- (void)testE0E1RAMConsistent {
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// Do some random language card paging, to hit set_language_card.
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_memoryMap.set_state_register(0x00);
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_memoryMap.set_state_register(0xff);
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[self write: 0x12 address:0xe0'0000];
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[self write: 0x34 address:0xe1'0000];
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XCTAssertEqual(_ram[_ram.size() - 128*1024], 0x12);
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XCTAssertEqual(_ram[_ram.size() - 64*1024], 0x34);
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}
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2020-12-12 02:30:03 +00:00
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- (void)testAuxiliarySwitches {
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// Inhibit IO/LC 'shadowing'.
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_memoryMap.set_shadow_register(0x40);
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// Check that all writes and reads currently occur to main RAM.
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XCTAssertEqual(_memoryMap.get_state_register() & 0xf0, 0x00);
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for(int c = 0; c < 65536; c++) {
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const uint8_t value = c ^ (c >> 8);
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[self write:value address:c];
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XCTAssertEqual(_ram[c], value);
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}
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// Reset.
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memset(_ram.data(), 0, 128*1024);
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// Set writing to auxiliary memory.
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// Reading should still be from main.
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_memoryMap.access(0xc005, false);
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XCTAssertEqual(_memoryMap.get_state_register() & 0xf0, 0x10);
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for(int c = 0x0200; c < 0xc000; c++) {
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const uint8_t value = c ^ (c >> 8);
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[self write:value address:c];
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XCTAssertEqual(_ram[c + 64*1024], value);
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XCTAssertEqual([self readAddress:c], 0);
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}
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// Reset.
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memset(_ram.data(), 0, 128*1024);
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// Switch reading and writing.
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_memoryMap.access(0xc004, false);
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_memoryMap.access(0xc003, false);
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XCTAssertEqual(_memoryMap.get_state_register() & 0xf0, 0x20);
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for(int c = 0x0200; c < 0xc000; c++) {
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const uint8_t value = c ^ (c >> 8);
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[self write:value address:c];
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XCTAssertEqual(_ram[c], value);
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XCTAssertEqual([self readAddress:c], 0);
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}
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// Reset.
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memset(_ram.data(), 0, 128*1024);
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// Test main zero page.
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for(int c = 0x0000; c < 0x0200; c++) {
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const uint8_t value = c ^ (c >> 8);
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[self write:value address:c];
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XCTAssertEqual(_ram[c], value);
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XCTAssertEqual([self readAddress:c], value);
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}
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// Reset.
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memset(_ram.data(), 0, 128*1024);
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// Enable the alternate zero page.
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_memoryMap.access(0xc009, false);
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XCTAssertEqual(_memoryMap.get_state_register() & 0xf0, 0xa0);
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for(int c = 0x0000; c < 0x0200; c++) {
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const uint8_t value = c ^ (c >> 8);
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[self write:value address:c];
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XCTAssertEqual(_ram[c + 64*1024], value);
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XCTAssertEqual([self readAddress:c], value);
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}
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// Reset.
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memset(_ram.data(), 0, 128*1024);
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// Enable 80STORE and PAGE2 and test for access to the second video page.
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_memoryMap.access(0xc001, false);
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_memoryMap.access(0xc055, true);
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XCTAssertEqual(_memoryMap.get_state_register() & 0xf0, 0xe0);
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for(int c = 0x0400; c < 0x0800; c++) {
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const uint8_t value = c ^ (c >> 8);
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[self write:value address:c];
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XCTAssertEqual(_ram[c + 64*1024], value);
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XCTAssertEqual([self readAddress:c], value);
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}
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// Reset.
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memset(_ram.data(), 0, 128*1024);
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// Enable HIRES and test for access to the second video page.
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_memoryMap.access(0xc057, true);
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for(int c = 0x2000; c < 0x4000; c++) {
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const uint8_t value = c ^ (c >> 8);
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[self write:value address:c];
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XCTAssertEqual(_ram[c + 64*1024], value);
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XCTAssertEqual([self readAddress:c], value);
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}
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}
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2022-06-26 01:41:37 +00:00
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- (void)testJSONExamples {
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NSArray<NSDictionary *> *const tests =
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[NSJSONSerialization JSONObjectWithData:
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[NSData dataWithContentsOfURL:
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[[NSBundle bundleForClass:[self class]]
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URLForResource:@"mm"
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withExtension:@"json"
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subdirectory:@"IIgs Memory Map"]]
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options:0
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error:nil];
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2022-06-27 15:16:05 +00:00
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[tests enumerateObjectsUsingBlock:^(NSDictionary * _Nonnull test, NSUInteger index, BOOL * _Nonnull stop) {
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NSLog(@"Test index %lu", static_cast<unsigned long>(index));
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2022-06-26 01:41:37 +00:00
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// Apply state.
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const bool highRes = [test[@"hires"] boolValue];
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const bool lcw = [test[@"lcw"] boolValue];
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const bool store80 = [test[@"80store"] boolValue];
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const uint8_t shadow = [test[@"shadow"] integerValue];
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const uint8_t state = [test[@"state"] integerValue];
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2022-06-27 01:20:57 +00:00
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_memoryMap.access(0xc056 + highRes, false);
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_memoryMap.access(0xc080 + lcw, false);
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_memoryMap.access(0xc080 + lcw, false);
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_memoryMap.access(0xc000 + store80, false);
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2022-06-26 01:41:37 +00:00
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_memoryMap.set_shadow_register(shadow);
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_memoryMap.set_state_register(state);
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// Test results.
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2022-06-28 20:22:41 +00:00
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auto testMemory =
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2022-06-28 20:32:35 +00:00
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^(NSString *type, void (^ applyTest)(int logical, int physical, const MemoryMap::Region ®ion)) {
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2022-06-28 20:22:41 +00:00
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for(NSArray<NSNumber *> *region in test[type]) {
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const auto logicalStart = [region[0] intValue];
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const auto logicalEnd = [region[1] intValue];
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const auto physicalStart = [region[2] intValue];
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const auto physicalEnd = [region[3] intValue];
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if(physicalEnd == physicalStart && physicalStart == 0) {
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continue;
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}
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2022-06-27 01:20:57 +00:00
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2022-06-28 20:22:41 +00:00
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int physical = physicalStart;
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for(int logical = logicalStart; logical < logicalEnd; logical++) {
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2022-06-28 20:32:35 +00:00
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const auto ®ion = self->_memoryMap.regions[self->_memoryMap.region_map[logical]];
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// Don't worry about IO pages here; they'll be compared shortly.
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if(!(region.flags & MemoryMap::Region::IsIO)) {
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const auto ®ion = self->_memoryMap.regions[self->_memoryMap.region_map[logical]];
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applyTest(logical, physical, region);
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if(*stop) {
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2022-06-28 20:57:09 +00:00
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NSLog(@"Logical page %04x should be mapped to %@ physical %04x",
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logical,
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type,
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physical);
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2022-06-28 20:32:35 +00:00
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NSLog(@"Stopping after first failure");
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return;
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}
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}
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2022-06-28 20:22:41 +00:00
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if(physical != physicalEnd) ++physical;
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}
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}
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};
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2022-06-27 01:49:58 +00:00
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2022-06-28 20:22:41 +00:00
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auto physicalOffset =
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^(const uint8_t *pointer) {
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2022-06-27 01:49:58 +00:00
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// Check for a mapping to RAM.
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2022-06-28 20:22:41 +00:00
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if(pointer >= self->_ram.data() && pointer < &(*self->_ram.end())) {
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int foundPhysical = int(pointer - self->_ram.data()) >> 8;
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2022-06-27 01:49:58 +00:00
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// This emulator maps a contiguous 8mb + 128kb of RAM such that the
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// first 8mb resides up to physical location 0x8000, and the final
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// 128kb sits from locatio 0xe000. So adjust for that here.
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if(foundPhysical >= 0x8000) {
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foundPhysical += 0xe000 - 0x8000;
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}
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2022-06-28 20:22:41 +00:00
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return foundPhysical;
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2022-06-27 01:49:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Check for a mapping to ROM.
|
2022-06-28 20:22:41 +00:00
|
|
|
if(pointer >= self->_rom.data() && pointer < &(*self->_rom.end())) {
|
2022-06-27 01:49:58 +00:00
|
|
|
// This emulator uses a separate store for ROM, which sholud appear in
|
|
|
|
// the memory map from locatio 0xfc00.
|
2022-06-28 20:22:41 +00:00
|
|
|
return 0xfc00 + (int(pointer - self->_rom.data()) >> 8);
|
2022-06-27 01:49:58 +00:00
|
|
|
}
|
|
|
|
|
2022-06-28 20:22:41 +00:00
|
|
|
return -1;
|
|
|
|
};
|
|
|
|
|
|
|
|
// Test read pointers.
|
2022-06-28 20:32:35 +00:00
|
|
|
testMemory(@"read", ^(int logical, int physical, const MemoryMap::Region ®ion) {
|
2022-06-28 20:22:41 +00:00
|
|
|
XCTAssert(region.read != nullptr);
|
2022-06-28 20:35:47 +00:00
|
|
|
if(region.read == nullptr) {
|
|
|
|
*stop = YES;
|
|
|
|
return;
|
|
|
|
}
|
2022-06-28 20:22:41 +00:00
|
|
|
|
|
|
|
// Compare to correct value.
|
2022-06-28 20:35:47 +00:00
|
|
|
const int foundPhysical = physicalOffset(®ion.read[logical << 8]);
|
2022-06-28 20:28:00 +00:00
|
|
|
if(physical != foundPhysical) {
|
|
|
|
*stop = YES;
|
2022-06-28 20:57:09 +00:00
|
|
|
return;
|
2022-06-28 20:28:00 +00:00
|
|
|
}
|
|
|
|
});
|
|
|
|
|
|
|
|
// Test write pointers.
|
2022-06-28 20:32:35 +00:00
|
|
|
testMemory(@"write", ^(int logical, int physical, const MemoryMap::Region ®ion) {
|
2022-06-28 20:28:00 +00:00
|
|
|
// This emulator guards writes to ROM by setting those pointers to nullptr;
|
|
|
|
// so allow a nullptr write target if ROM is mapped here.
|
|
|
|
if(region.write == nullptr && physical >= 0xfc00) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2022-06-28 20:57:09 +00:00
|
|
|
// Questionable test results: I'm not sure the source is correct in its
|
|
|
|
// handling of language card read access. Don't test that.
|
|
|
|
//
|
|
|
|
// This test set treats the language card write flip flop as _enabling_
|
|
|
|
// writes. I think it _disables_ writes. TODO: reconcile.
|
|
|
|
if(
|
|
|
|
(logical >= 0x00d0 && logical < 0x0100) ||
|
|
|
|
(logical >= 0x01d0 && logical < 0x0200) ||
|
|
|
|
(logical >= 0xe0d0 && logical < 0xe100) ||
|
|
|
|
(logical >= 0xe1d0 && logical < 0xe200)
|
|
|
|
) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2022-06-28 20:28:00 +00:00
|
|
|
XCTAssert(region.write != nullptr);
|
2022-06-28 20:35:47 +00:00
|
|
|
if(region.write == nullptr) {
|
|
|
|
*stop = YES;
|
|
|
|
return;
|
|
|
|
}
|
2022-06-28 20:28:00 +00:00
|
|
|
|
|
|
|
// Compare to correct value.
|
2022-06-28 20:35:47 +00:00
|
|
|
const int foundPhysical = physicalOffset(®ion.write[logical << 8]);
|
2022-06-28 20:22:41 +00:00
|
|
|
if(physical != foundPhysical) {
|
|
|
|
*stop = YES;
|
2022-06-28 20:57:09 +00:00
|
|
|
return;
|
2022-06-26 01:41:37 +00:00
|
|
|
}
|
2022-06-28 20:22:41 +00:00
|
|
|
});
|
2022-06-27 15:16:05 +00:00
|
|
|
}];
|
2022-06-26 01:41:37 +00:00
|
|
|
}
|
|
|
|
|
2020-10-26 01:31:21 +00:00
|
|
|
@end
|