2021-11-09 12:11:23 +00:00
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//
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// Audio.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 09/11/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef Audio_hpp
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#define Audio_hpp
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#include "DMADevice.hpp"
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2021-11-11 14:24:15 +00:00
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#include "../../ClockReceiver/ClockReceiver.hpp"
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#include "../../Concurrency/AsyncTaskQueue.hpp"
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2021-11-09 12:11:23 +00:00
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namespace Amiga {
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class Audio: public DMADevice<4> {
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public:
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2021-11-11 14:24:15 +00:00
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Audio(
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Chipset &chipset, uint16_t *ram, size_t word_size,
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[[maybe_unused]] double output_rate) :
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DMADevice<4>(chipset, ram, word_size) {}
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2021-11-09 12:11:23 +00:00
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2021-11-11 14:24:15 +00:00
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/// Idiomatic call-in for DMA scheduling; indicates that this class may
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/// perform a DMA access for the stated channel now.
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2021-11-13 20:53:41 +00:00
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bool advance_dma(int channel);
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2021-11-09 12:11:23 +00:00
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2021-11-13 20:53:41 +00:00
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/// Advances output by one DMA window, which is implicitly two cycles
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/// at the output rate that was specified to the constructor.
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void output();
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2021-11-11 14:24:15 +00:00
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/// Sets the total number of words to fetch for the given channel.
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void set_length(int channel, uint16_t);
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/// Sets the number of DMA windows between each 8-bit output,
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/// in the same time base as @c ticks_per_line.
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void set_period(int channel, uint16_t);
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/// Sets the output volume for the given channel; if bit 6 is set
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/// then output is maximal; otherwise bits 0–5 select
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/// a volume of [0–63]/64, on a logarithmic scale.
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void set_volume(int channel, uint16_t);
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/// Sets the next two samples of audio to output.
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void set_data(int channel, uint16_t);
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/// Provides a copy of the DMA enable flags, for the purpose of
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/// determining which channels are enabled for DMA.
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void set_channel_enables(uint16_t);
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/// Sets which channels, if any, modulate period or volume of
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/// their neighbours.
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void set_modulation_flags(uint16_t);
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2021-11-13 16:05:39 +00:00
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/// Sets which interrupt requests are currently active.
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void set_interrupt_requests(uint16_t);
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2021-11-11 14:24:15 +00:00
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private:
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struct Channel {
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// The data latch plus a count of unused samples
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// in the latch, which will always be 0, 1 or 2.
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uint16_t data = 0x0000;
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bool has_data = false;
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uint16_t data_latch = 0x0000;
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// Number of words remaining in DMA data.
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uint16_t length = 0;
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uint16_t length_counter = 0;
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// Number of ticks between each sample, plus the
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// current counter, which counts downward.
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uint16_t period = 0;
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uint16_t period_counter = 0;
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// Output volume, [0, 64].
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uint8_t volume;
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// Indicates whether DMA is enabled for this channel.
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bool dma_enabled = false;
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// Records whether this audio interrupt is pending.
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bool interrupt_pending = false;
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bool will_request_interrupt = false;
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2021-11-12 20:30:52 +00:00
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// Replicates the Hardware Reference Manual state machine;
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// comments indicate which of the documented states each
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// label refers to.
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enum class State {
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Disabled, // 000
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WaitingForDummyDMA, // 001
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WaitingForDMA, // 101
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PlayingHigh, // 010
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PlayingLow, // 011
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} state = State::Disabled;
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bool output();
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2021-11-15 10:29:28 +00:00
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template <State state> bool output();
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template <State begin, State end> bool transit();
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} channels_[4];
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};
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}
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#endif /* Audio_hpp */
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