2020-09-24 02:14:42 +00:00
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//
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// 65816Storage.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 23/09/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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2020-09-25 02:27:20 +00:00
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#include "../65816.hpp"
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2020-09-24 02:14:42 +00:00
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2020-09-25 02:27:20 +00:00
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using namespace CPU::WDC65816;
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2020-09-25 02:27:20 +00:00
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struct CPU::WDC65816::ProcessorStorageConstructor {
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2020-09-24 21:36:11 +00:00
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/*
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Code below is structured to ease translation from Table 5-7 of the 2018
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edition of the WDC 65816 datasheet.
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In each case the relevant addressing mode is described here via a generator
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function that will spit out the correct MicroOps based on access type
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(i.e. read, write or read-modify-write) and data size (8- or 16-bit).
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That leads up to being able to declare the opcode map by addressing mode
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and operation alone.
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Things the generators can assume before they start:
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1) the opcode has already been fetched and decoded, and the program counter incremented;
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2) the data buffer is empty; and
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3) the data address is undefined.
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*/
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// 1a. Absolute a.
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static void absolute(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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if(type == AccessType::Write) {
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target(OperationPerform); // Perform operation to fill the data buffer.
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target(CycleStoreIncrementData); // Data low.
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if(is8bit) target(CycleStoreIncrementData); // Data high.
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} else {
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target(CycleFetchIncrementData); // Data low.
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if(is8bit) target(CycleFetchIncrementData); // Data high.
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target(OperationPerform); // Perform operation from the data buffer.
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}
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};
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2020-09-24 02:23:23 +00:00
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// 1b. Absolute a, JMP.
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static void absolute_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchPC); // New PCH.
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target(OperationConstructAbsolute); // Calculate data address.
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target(OperationPerform); // [JMP]
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};
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// 1c. Absolute a, JSR.
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static void absolute_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchPC); // New PCH.
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target(CycleFetchPC); // IO
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target(OperationConstructAbsolute); // Calculate data address.
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target(OperationPerform); // [JSR]
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target(CyclePush); // PCH
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target(CyclePush); // PCL
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};
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2020-09-24 02:28:15 +00:00
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// 1d. Absolute read-modify-write.
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static void absolute_rmw(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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if(!is8bit) target(CycleFetchIncrementData); // Data low.
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target(CycleFetchData); // Data [high].
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if(!is8bit) target(CycleFetchData); // 16-bit: reread final byte of data.
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else target(CycleStoreData); // 8-bit rewrite final byte of data.
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target(OperationPerform); // Perform operation within the data buffer.
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if(!is8bit) target(CycleStoreDecrementData); // Data high.
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target(CycleStoreData); // Data [low].
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};
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// 2a. Absolute Indexed Indirect (a, x), JMP.
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static void absolute_indexed_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchPC); // AAH.
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target(CycleFetchPC); // IO.
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target(OperationConstructAbsoluteIndexedIndirect); // Calculate data address.
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target(CycleFetchIncrementData); // New PCL
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target(CycleFetchData); // New PCH.
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target(OperationPerform); // [JMP]
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};
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// 2b. Absolute Indexed Indirect (a, x), JSR.
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static void absolute_indexed_indirect_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(OperationCopyPCToData); // Prepare to push.
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target(CyclePush); // PCH
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target(CyclePush); // PCL
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target(CycleFetchPC); // AAH.
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target(CycleFetchPC); // IO.
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target(OperationConstructAbsoluteIndexedIndirect); // Calculate data address.
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target(CycleFetchIncrementData); // New PCL
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target(CycleFetchData); // New PCH.
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target(OperationPerform); // [JSR]
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}
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};
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AccessType ProcessorStorage::access_type_for_operation(Operation operation) {
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switch(operation) {
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case ADC: case AND: case BIT: case CMP:
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case CPX: case CPY: case EOR: case ORA:
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case SBC:
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case LDA: case LDX: case LDY:
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case JMP: case JSR:
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return AccessType::Read;
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case STA: case STX: case STY: case STZ:
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return AccessType::Write;
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}
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}
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void ProcessorStorage::install(void (* generator)(AccessType, bool, const std::function<void(MicroOp)>&), Operation operation, ProcessorStorageConstructor &) {
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const AccessType access_type = access_type_for_operation(operation);
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(*generator)(access_type, true, [] (MicroOp) {});
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// TODO:
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// (1) use [hash of] pointer to generator to determine whether operation tables have already been built;
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// (2) if not, build them in both 8- and 16-bit variations;
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// (3) insert appropriate entries into an instruction table for the current instruction; and
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// (4) increment the instruction counter.
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//
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// Additional observation: temporary storage would be helpful, so load that into ProcessorStorageConstructor.
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}
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ProcessorStorage::ProcessorStorage() {
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ProcessorStorageConstructor constructor;
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// Install the instructions.
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#define op(x, y) install(&ProcessorStorageConstructor::x, y, constructor)
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/* 0x00 BRK s */
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/* 0x01 ORA (d, x) */
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/* 0x02 COP s */
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/* 0x03 ORA d, s */
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/* 0x04 TSB d */
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/* 0x05 ORA d */
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/* 0x06 ASL d */
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/* 0x07 ORA [d] */
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/* 0x08 PHP s */
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/* 0x09 ORA # */
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/* 0x0a ASL a */
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/* 0x0b PHD s */
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/* 0x0c TSB a */
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/* 0x0d ORA a */ op(absolute, ORA);
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/* 0x0e ASL a */
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/* 0x0f ORA al */
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/* 0x10 BPL r */
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/* 0x11 ORA (d), y */
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/* 0x12 ORA (d) */
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/* 0x13 ORA (d, s), y */
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/* 0x14 TRB d */
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/* 0x15 ORA d,x */
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/* 0x16 ASL d, x */
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/* 0x17 ORA [d], y */
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/* 0x18 CLC i */
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/* 0x19 ORA a, y */
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/* 0x1a INC A */
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/* 0x1b TCS i */
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/* 0x1c TRB a */
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/* 0x1d ORA a, x */
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/* 0x1e ASL a, x */
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/* 0x1f ORA al, x */
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/* 0x20 JSR a */ op(absolute_jsr, JSR);
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/* 0x21 ORA (d), y */
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/* 0x22 AND (d, x) */
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/* 0x23 JSL al */
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/* 0x24 BIT d */
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/* 0x25 AND d */
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/* 0x26 ROL d */
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/* 0x27 AND [d] */
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/* 0x28 PLP s */
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/* 0x29 AND # */
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/* 0x2a ROL A */
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/* 0x2b PLD s */
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/* 0x2c BIT a */ op(absolute, BIT);
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/* 0x2d AND a */ op(absolute, AND);
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/* 0x2e ROL a */
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/* 0x2f AND al */
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/* 0x30 BMI R */
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/* 0x31 AND (d), y */
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/* 0x32 AND (d) */
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/* 0x33 AND (d, s), y */
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/* 0x34 BIT d, x */
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/* 0x35 AND d, x */
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/* 0x36 TOL d, x */
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/* 0x37 AND [d], y */
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/* 0x38 SEC i */
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/* 0x39 AND a, y */
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/* 0x3a DEC A */
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/* 0x3b TSC i */
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/* 0x3c BIT a, x */
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/* 0x3d AND a, x */
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/* 0x3e TLD a, x */
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/* 0x3f AND al, x */
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/* 0x40 RTI s */
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/* 0x41 EOR (d, x) */
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/* 0x42 WDM i */
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/* 0x43 EOR d, s */
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/* 0x44 MVP xyc */
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/* 0x45 EOR d */
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/* 0x46 LSR d */
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/* 0x47 EOR [d] */
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/* 0x48 PHA s */
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/* 0x49 EOR # */
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/* 0x4a LSR A */
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/* 0x4b PHK s */
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/* 0x4c JMP a */ op(absolute, JMP);
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/* 0x4d EOR a */ op(absolute, EOR);
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/* 0x4e LSR a */
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/* 0x4f EOR Al */
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/* 0x50 BVC r */
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/* 0x51 EOR (d), y */
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/* 0x52 EOR (d) */
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/* 0x53 EOR (d, s), y */
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/* 0x54 MVN xyc */
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/* 0x55 EOR d, x */
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/* 0x56 LSR d, x */
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/* 0x57 EOR [d],y */
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/* 0x58 CLI i */
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/* 0x59 EOR a, y */
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/* 0x5a PHY s */
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/* 0x5b TCD i */
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/* 0x5c JMP al */
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/* 0x5d EOR a, x */
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/* 0x5e LSR a, x */
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/* 0x5f EOR al, x */
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/* 0x60 RTS s */
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/* 0x61 ADC (d, x) */
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/* 0x62 PER s */
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/* 0x63 ADC d, s */
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/* 0x64 STZ d */
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/* 0x65 ADC d */
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/* 0x66 ROR d */
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/* 0x67 ADC [d] */
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/* 0x68 PLA s */
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/* 0x69 ADC # */
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/* 0x6a ROR A */
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/* 0x6b RTL s */
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/* 0x6c JMP (a) */
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/* 0x6d ADC a */ op(absolute, ADC);
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/* 0x6e ROR a */
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/* 0x6f ADC al */
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/* 0x70 BVS r */
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/* 0x71 ADC (d), y */
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/* 0x72 ADC (d) */
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/* 0x73 ADC (d, s), y */
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/* 0x74 STZ d, x */
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/* 0x75 ADC d, x */
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/* 0x76 ROR d, x */
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/* 0x77 ADC [d], y */
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/* 0x78 SEI i */
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/* 0x79 ADC a, y */
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/* 0x7a PLY s */
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/* 0x7b TDC i */
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/* 0x7c JMP (a, x) */ op(absolute_indexed_indirect_jmp, JMP);
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/* 0x7d ADC a, x */
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/* 0x7e ROR a, x */
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/* 0x7f ADC al, x */
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/* 0x80 BRA r */
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/* 0x81 STA (d, x) */
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/* 0x82 BRL rl */
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/* 0x83 STA d, s */
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/* 0x84 STY d */
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/* 0x85 STA d */
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/* 0x86 STX d */
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/* 0x87 STA [d] */
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/* 0x88 DEY i */
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/* 0x89 BIT # */
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/* 0x8a TXA i */
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/* 0x8b PHB s */
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/* 0x8c STY a */ op(absolute, STY);
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/* 0x8d STA a */ op(absolute, STA);
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/* 0x8e STX a */ op(absolute, STX);
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/* 0x8f STA al */
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/* 0x90 BCC r */
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/* 0x91 STA (d), y */
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/* 0x92 STA (d) */
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/* 0x93 STA (d, x), y */
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/* 0x94 STY d, x */
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/* 0x95 STA d, x */
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/* 0x96 STX d, y */
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/* 0x97 STA [d], y */
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/* 0x98 TYA i */
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/* 0x99 STA a, y */
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/* 0x9a TXS i */
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/* 0x9b TXY i */
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/* 0x9c STZ a */ op(absolute, STZ);
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/* 0x9d STA a, x */
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/* 0x9e STZ a, x */
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/* 0x9f STA al, x */
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/* 0xa0 LDY # */
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/* 0xa1 LDA (d, x) */
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/* 0xa2 LDX # */
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/* 0xa3 LDA d, s */
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/* 0xa4 LDY d */
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/* 0xa5 LDA d */
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/* 0xa6 LDX d */
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/* 0xa7 LDA [d] */
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/* 0xa8 TAY i */
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/* 0xa9 LDA # */
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/* 0xaa TAX i */
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/* 0xab PLB s */
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2020-09-25 02:27:20 +00:00
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/* 0xac LDY a */ op(absolute, LDY);
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/* 0xad LDA a */ op(absolute, LDA);
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/* 0xae LDX a */ op(absolute, LDX);
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2020-09-24 02:14:42 +00:00
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/* 0xaf LDA al */
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/* 0xb0 BCS r */
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/* 0xb1 LDA (d), y */
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/* 0xb2 LDA (d) */
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/* 0xb3 LDA (d, s), y */
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/* 0xb4 LDY d, x */
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/* 0xb5 LDA d, x */
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/* 0xb6 LDX d, y */
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/* 0xb7 LDA [d], y */
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/* 0xb8 CLV i */
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/* 0xb9 LDA a, y */
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/* 0xba TSX i */
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/* 0xbb TYX i */
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/* 0xbc LDY a, x */
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/* 0xbd LDA a, x */
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/* 0xbe LDX a, y */
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/* 0xbf LDA al, x */
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/* 0xc0 CPY # */
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/* 0xc1 CMP (d, x) */
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/* 0xc2 REP # */
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/* 0xc3 CMP d, s */
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/* 0xc4 CPY d */
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/* 0xc5 CMP d */
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/* 0xc6 DEC d */
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/* 0xc7 CMP [d] */
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/* 0xc8 INY i */
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/* 0xc9 CMP # */
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/* 0xca DEX i */
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/* 0xcb WAI i */
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2020-09-25 02:27:20 +00:00
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/* 0xcc CPY a */ op(absolute, CPY);
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/* 0xcd CMP a */ op(absolute, CMP);
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2020-09-24 02:14:42 +00:00
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/* 0xce DEC a */
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/* 0xcf CMP al */
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/* 0xd0 BNE r */
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/* 0xd1 CMP (d), y */
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/* 0xd2 CMP (d) */
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/* 0xd3 CMP (d, s), y */
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/* 0xd4 PEI s */
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/* 0xd5 CMP d, x */
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/* 0xd6 DEC d, x */
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/* 0xd7 CMP [d], y */
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/* 0xd8 CLD i */
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/* 0xd9 CMP a, y */
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/* 0xda PHX s */
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/* 0xdb STP i */
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/* 0xdc JMP (a) */
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/* 0xdd CMP a, x */
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/* 0xde DEC a, x */
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/* 0xdf CMP al, x */
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/* 0xe0 CPX # */
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/* 0xe1 SBC (d, x) */
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/* 0xe2 SEP # */
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/* 0xe3 SBC d, s */
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/* 0xe4 CPX d */
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/* 0xe5 SBC d */
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/* 0xe6 INC d */
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/* 0xe7 SBC [d] */
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/* 0xe8 INX i */
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/* 0xe9 SBC # */
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/* 0xea NOP i */
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/* 0xeb XBA i */
|
2020-09-25 02:27:20 +00:00
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/* 0xec CPX a */ op(absolute, CPX);
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/* 0xed SBC a */ op(absolute, SBC);
|
2020-09-24 02:14:42 +00:00
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/* 0xee INC a */
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/* 0xef SBC al */
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/* 0xf0 BEQ r */
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/* 0xf1 SBC (d), y */
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/* 0xf2 SBC (d) */
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/* 0xf3 SBC (d, s), y */
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/* 0xf4 PEA s */
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/* 0xf5 SBC d, x */
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/* 0xf6 INC d, x */
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/* 0xf7 SBC [d], y */
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/* 0xf8 SED i */
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/* 0xf9 SBC a, y */
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/* 0xfa PLX s */
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/* 0xfb XCE i */
|
2020-09-25 02:37:31 +00:00
|
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/* 0xfc JSR (a, x) */ op(absolute_indexed_indirect_jsr, JSR);
|
2020-09-24 02:14:42 +00:00
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/* 0xfd SBC a, x */
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/* 0xfe INC a, x */
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/* 0xff SBC al, x */
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#undef op
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}
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