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CLK/Processors/Z80/AllRAM/Z80AllRAM.hpp

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Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
2017-05-17 01:19:17 +00:00
//
// Z80AllRAM.hpp
// Clock Signal
//
// Created by Thomas Harte on 16/05/2017.
Removes all instances of the copyright symbol.
2018-05-13 19:19:52 +00:00
// Copyright 2017 Thomas Harte. All rights reserved.
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
2017-05-17 01:19:17 +00:00
//
#ifndef Z80AllRAM_hpp
#define Z80AllRAM_hpp
Refactors the Z80 to separate out interface and implementation. Following the pattern just established by the 6502, puts all implementation specifics beyond the visibility of a human reading Z80.hpp and in subfolders so as to promote the idea that they shouldn't go out of their way.
2017-09-02 00:50:24 +00:00
#include "../Z80.hpp"
#include "../../AllRAMProcessor.hpp"
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
2017-05-17 01:19:17 +00:00
namespace CPU {
namespace Z80 {
Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
2017-05-17 01:28:17 +00:00
class AllRAMProcessor:
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
2017-05-31 02:41:23 +00:00
public ::CPU::AllRAMProcessor {
Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
2017-05-17 01:28:17 +00:00
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
2017-05-17 01:19:17 +00:00
public:
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
2017-05-31 02:41:23 +00:00
static AllRAMProcessor *Processor();
Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
2017-05-22 23:24:11 +00:00
struct MemoryAccessDelegate {
Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
2017-07-28 00:17:13 +00:00
virtual void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, HalfCycles time_stamp) = 0;
Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
2017-05-22 23:24:11 +00:00
};
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
2017-05-31 02:41:23 +00:00
inline void set_memory_access_delegate(MemoryAccessDelegate *delegate) {
Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
2017-05-22 23:24:11 +00:00
delegate_ = delegate;
}
Standardises on `const [Half]Cycles` as the thing called and returned, rather than `const [Half]Cycles &` as it's explicitly defined to be only one `int` in size, so using a reference is overly weighty.
2017-07-28 02:05:29 +00:00
virtual void run_for(const Cycles cycles) = 0;
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
2017-05-31 02:41:23 +00:00
virtual uint16_t get_value_of_register(Register r) = 0;
virtual void set_value_of_register(Register r, uint16_t value) = 0;
virtual bool get_halt_line() = 0;
Minor syntax and wiring fixes.
2017-06-02 02:33:05 +00:00
virtual void reset_power_on() = 0;
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
2017-06-23 01:09:26 +00:00
Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
2017-06-03 21:41:45 +00:00
virtual void set_interrupt_line(bool value) = 0;
virtual void set_non_maskable_interrupt_line(bool value) = 0;
Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
2017-06-23 01:09:26 +00:00
virtual void set_wait_line(bool value) = 0;
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
2017-05-31 02:41:23 +00:00
protected:
Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
2017-05-22 23:24:11 +00:00
MemoryAccessDelegate *delegate_;
Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
2017-05-31 02:41:23 +00:00
AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {}
Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
2017-05-17 01:19:17 +00:00
};
}
}
#endif /* Z80AllRAM_hpp */
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