mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-22 12:33:29 +00:00
Implement the complete set of fetch addressing modes.
Subject to observations: (1) MOVE uses slightly custom versions of many of these for its stores; and (2) PEA and LEA need to do the calculation but not the read, so some of this will be duplicated further. It's either that or include greater conditionality on the path.
This commit is contained in:
Thomas Harte
parent
e4c0a89889
commit
0471decfc8
@ -258,9 +258,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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next_operand_ = 0;
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// Obtain operand flags and pick a perform pattern.
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#define CASE(x, y) \
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#define CASE(x) \
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case InstructionSet::M68k::Operation::x: \
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operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>(); \
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operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>();
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#define StdCASE(x, y) \
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CASE(x) \
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y; \
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\
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if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::LongWord) { \
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@ -276,7 +279,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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}
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switch(instruction_.operation) {
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CASE(NBCD, {
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StdCASE(NBCD, {
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if(instruction_.mode(0) == Mode::DataRegisterDirect) {
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perform_state_ = Perform_np_n;
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} else {
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@ -284,17 +287,20 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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}
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})
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CASE(SWAP, perform_state_ = Perform_np);
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StdCASE(SWAP, perform_state_ = Perform_np);
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CASE(MOVEw, perform_state_ = MOVEw);
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StdCASE(MOVEw, perform_state_ = MOVEw);
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CASE(CMPb, perform_state_ = Perform_np);
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CASE(CMPw, perform_state_ = Perform_np);
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CASE(CMPl, perform_state_ = Perform_np_n);
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StdCASE(CMPb, perform_state_ = Perform_np);
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StdCASE(CMPw, perform_state_ = Perform_np);
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StdCASE(CMPl, perform_state_ = Perform_np_n);
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CASE(ANDb, perform_state_ = Perform_np);
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CASE(ANDw, perform_state_ = Perform_np);
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CASE(ANDl, {
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StdCASE(CMPAw, perform_state_ = Perform_np_n);
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StdCASE(CMPAl, perform_state_ = Perform_np_n);
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StdCASE(ANDb, perform_state_ = Perform_np);
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StdCASE(ANDw, perform_state_ = Perform_np);
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StdCASE(ANDl, {
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if(instruction_.mode(1) == Mode::DataRegisterDirect) {
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switch(instruction_.mode(0)) {
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default:
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@ -310,9 +316,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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}
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});
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CASE(ORb, perform_state_ = Perform_np);
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CASE(ORw, perform_state_ = Perform_np);
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CASE(ORl, {
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StdCASE(ORb, perform_state_ = Perform_np);
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StdCASE(ORw, perform_state_ = Perform_np);
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StdCASE(ORl, {
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if(instruction_.mode(1) == Mode::DataRegisterDirect) {
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switch(instruction_.mode(0)) {
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default:
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@ -328,9 +334,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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}
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});
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CASE(EORb, perform_state_ = Perform_np);
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CASE(EORw, perform_state_ = Perform_np);
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CASE(EORl, {
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StdCASE(EORb, perform_state_ = Perform_np);
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StdCASE(EORw, perform_state_ = Perform_np);
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StdCASE(EORl, {
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if(instruction_.mode(1) == Mode::DataRegisterDirect) {
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perform_state_ = Perform_np_nn;
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} else {
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@ -452,6 +458,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// MARK: - Fetch, addressing modes.
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//
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// AddressRegisterIndirect
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//
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BeginState(FetchAddressRegisterIndirect_bw):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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SetDataAddress(effective_address_[next_operand_]);
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@ -459,7 +468,6 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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// TODO: avoid use of temporary_address_ here and probably above.
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BeginState(FetchAddressRegisterIndirect_l):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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SetDataAddress(effective_address_[next_operand_]);
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@ -470,6 +478,217 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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//
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// AddressRegisterIndirectWithPostincrement
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//
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BeginState(FetchAddressRegisterIndirectWithPostincrement_bw):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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registers_[8 + instruction_.reg(next_operand_)].l +=
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byte_word_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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SetDataAddress(effective_address_[next_operand_]);
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchAddressRegisterIndirectWithPostincrement_l):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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registers_[8 + instruction_.reg(next_operand_)].l += 4;
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SetDataAddress(effective_address_[next_operand_]);
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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//
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// AddressRegisterIndirectWithPredecrement
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//
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BeginState(FetchAddressRegisterIndirectWithPredecrement_bw):
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registers_[8 + instruction_.reg(next_operand_)].l -=
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byte_word_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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SetDataAddress(effective_address_[next_operand_]);
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IdleBus(1); // n
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchAddressRegisterIndirectWithPredecrement_l):
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registers_[8 + instruction_.reg(next_operand_)].l -= 4;
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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SetDataAddress(effective_address_[next_operand_]);
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IdleBus(1); // n
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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//
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// AddressRegisterIndirectWithDisplacement
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//
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BeginState(FetchAddressRegisterIndirectWithDisplacement_bw):
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effective_address_[next_operand_] =
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registers_[8 + instruction_.reg(next_operand_)].l +
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int16_t(prefetch_.w);
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SetDataAddress(effective_address_[next_operand_]);
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Prefetch(); // np
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchAddressRegisterIndirectWithDisplacement_l):
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effective_address_[next_operand_] =
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registers_[8 + instruction_.reg(next_operand_)].l +
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int16_t(prefetch_.w);
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SetDataAddress(effective_address_[next_operand_]);
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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//
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// ProgramCounterIndirectWithDisplacement
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//
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BeginState(FetchProgramCounterIndirectWithDisplacement_bw):
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effective_address_[next_operand_] =
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instruction_address_ + 2 +
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int16_t(prefetch_.w);
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SetDataAddress(effective_address_[next_operand_]);
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Prefetch(); // np
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchProgramCounterIndirectWithDisplacement_l):
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effective_address_[next_operand_] =
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instruction_address_ + 2 +
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int16_t(prefetch_.w);
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SetDataAddress(effective_address_[next_operand_]);
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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#define d8Xn(base) \
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base + \
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((prefetch_.w & 0x800) ? \
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registers_[prefetch_.w >> 12].l : \
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int16_t(registers_[prefetch_.w >> 12].w)) + \
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int8_t(prefetch_.b);
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//
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// AddressRegisterIndirectWithIndex8bitDisplacement
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//
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BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw):
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effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
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SetDataAddress(effective_address_[next_operand_]);
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IdleBus(1); // n
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Prefetch(); // np
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l):
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effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
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SetDataAddress(effective_address_[next_operand_]);
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IdleBus(1); // n
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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//
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// ProgramCounterIndirectWithIndex8bitDisplacement
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//
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BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw):
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effective_address_[next_operand_] = d8Xn(instruction_address_ + 2);
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SetDataAddress(effective_address_[next_operand_]);
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IdleBus(1); // n
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Prefetch(); // np
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l):
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effective_address_[next_operand_] = d8Xn(instruction_address_ + 2);;
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SetDataAddress(effective_address_[next_operand_]);
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IdleBus(1); // n
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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#undef d8Xn
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//
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// AbsoluteShort
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//
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BeginState(FetchAbsoluteShort_bw):
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effective_address_[next_operand_] = int16_t(prefetch_.w);
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SetDataAddress(effective_address_[next_operand_]);
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Prefetch(); // np
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchAbsoluteShort_l):
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effective_address_[next_operand_] = int16_t(prefetch_.w);
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SetDataAddress(effective_address_[next_operand_]);
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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//
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// AbsoluteLong
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//
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BeginState(FetchAbsoluteLong_bw):
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Prefetch(); // np
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effective_address_[next_operand_] = prefetch_.l;
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SetDataAddress(effective_address_[next_operand_]);
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Prefetch(); // np
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchAbsoluteLong_l):
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Prefetch(); // np
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effective_address_[next_operand_] = prefetch_.l;
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SetDataAddress(effective_address_[next_operand_]);
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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//
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// ImmediateData
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//
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BeginState(FetchImmediateData_bw):
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operand_[next_operand_].w = prefetch_.w;
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Prefetch(); // np
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchImmediateData_l):
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Prefetch(); // np
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operand_[next_operand_].l = prefetch_.l;
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Prefetch(); // np
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MoveToNextOperand(FetchOperand_l);
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// MARK: - Store.
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// Store operand is a lot simpler: only one operand is ever stored, and its address
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@ -563,25 +782,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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#define TODOState(x) \
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BeginState(x): [[fallthrough]];
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TODOState(FetchAddressRegisterIndirectWithPostincrement_bw);
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TODOState(FetchAddressRegisterIndirectWithPredecrement_bw);
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TODOState(FetchAddressRegisterIndirectWithDisplacement_bw);
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TODOState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw);
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TODOState(FetchProgramCounterIndirectWithDisplacement_bw);
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TODOState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw);
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TODOState(FetchAbsoluteShort_bw);
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TODOState(FetchAbsoluteLong_bw);
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TODOState(FetchImmediateData_bw);
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TODOState(FetchAddressRegisterIndirectWithPostincrement_l);
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TODOState(FetchAddressRegisterIndirectWithPredecrement_l);
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TODOState(FetchAddressRegisterIndirectWithDisplacement_l);
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TODOState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l);
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TODOState(FetchProgramCounterIndirectWithDisplacement_l);
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TODOState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l);
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TODOState(FetchAbsoluteShort_l);
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TODOState(FetchAbsoluteLong_l);
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TODOState(FetchImmediateData_l);
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// TODOState(FetchImmediateData_l);
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#undef TODOState
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@ -84,6 +84,11 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
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// Flow controller... all TODO.
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using Preinstruction = InstructionSet::M68k::Preinstruction;
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static constexpr uint32_t byte_word_increments[2][8] = {
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{ 1, 1, 1, 1, 1, 1, 1, 2, },
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{ 2, 2, 2, 2, 2, 2, 2, 2, }
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};
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template <typename IntT> void did_mulu(IntT) {}
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template <typename IntT> void did_muls(IntT) {}
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void did_chk(bool, bool) {}
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