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0471decfc8
Subject to observations: (1) MOVE uses slightly custom versions of many of these for its stores; and (2) PEA and LEA need to do the calculation but not the read, so some of this will be duplicated further. It's either that or include greater conditionality on the path.
868 lines
28 KiB
C++
868 lines
28 KiB
C++
//
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// 68000Mk2Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef _8000Mk2Implementation_h
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#define _8000Mk2Implementation_h
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#include <cassert>
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#include <cstdio>
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namespace CPU {
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namespace MC68000Mk2 {
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/// States for the state machine which are named by
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/// me for their purpose rather than automatically by file position.
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/// These are negative to avoid ambiguity with the other group.
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enum ExecutionState: int {
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Reset = std::numeric_limits<int>::min(),
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Decode,
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WaitForDTACK,
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/// Perform the proper sequence to fetch a byte or word operand.
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FetchOperand_bw,
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/// Perform the proper sequence to fetch a long-word operand.
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FetchOperand_l,
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StoreOperand,
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StoreOperand_l,
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// Specific addressing mode fetches.
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FetchAddressRegisterIndirect_bw,
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FetchAddressRegisterIndirectWithPostincrement_bw,
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FetchAddressRegisterIndirectWithPredecrement_bw,
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FetchAddressRegisterIndirectWithDisplacement_bw,
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FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw,
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FetchProgramCounterIndirectWithDisplacement_bw,
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FetchProgramCounterIndirectWithIndex8bitDisplacement_bw,
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FetchAbsoluteShort_bw,
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FetchAbsoluteLong_bw,
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FetchImmediateData_bw,
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FetchAddressRegisterIndirect_l,
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FetchAddressRegisterIndirectWithPostincrement_l,
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FetchAddressRegisterIndirectWithPredecrement_l,
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FetchAddressRegisterIndirectWithDisplacement_l,
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FetchAddressRegisterIndirectWithIndex8bitDisplacement_l,
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FetchProgramCounterIndirectWithDisplacement_l,
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FetchProgramCounterIndirectWithIndex8bitDisplacement_l,
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FetchAbsoluteShort_l,
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FetchAbsoluteLong_l,
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FetchImmediateData_l,
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// Various forms of perform; each of these will
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// perform the current instruction, then do the
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// indicated bus cycle.
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Perform_np,
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Perform_np_n,
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Perform_np_nn,
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// MOVE has unique bus usage, so has specialised states.
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MOVEw,
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MOVEwRegisterDirect,
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MOVEwAddressRegisterIndirectWithPostincrement,
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};
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// MARK: - The state machine.
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template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
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void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::run_for(HalfCycles duration) {
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// Accumulate the newly paid-in cycles. If this instance remains in deficit, exit.
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time_remaining_ += duration;
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if(time_remaining_ <= HalfCycles(0)) return;
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// Check whether all remaining time has been expended; if so then exit, having set this line up as
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// the next resumption point.
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#define ConsiderExit() if(time_remaining_ <= HalfCycles(0)) { state_ = __COUNTER__+1; return; } [[fallthrough]]; case __COUNTER__:
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// Subtracts `n` half-cycles from `time_remaining_`; if permit_overrun is false, also ConsiderExit()
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#define Spend(n) time_remaining_ -= (n); if constexpr (!permit_overrun) ConsiderExit()
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// Performs ConsiderExit() only if permit_overrun is true.
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#define CheckOverrun() if constexpr (permit_overrun) ConsiderExit()
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// Sets `x` as the next state, and exits now if all remaining time has been extended and permit_overrun is true.
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// Jumps directly to the state otherwise.
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#define MoveToState(x) { state_ = ExecutionState::x; goto x; }
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// Sets the start position for state x.
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#define BeginState(x) case ExecutionState::x: [[maybe_unused]] x
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//
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// So basic structure is, in general:
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//
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// BeginState(Action):
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// do_something();
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// Spend(20);
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// do_something_else();
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// Spend(10);
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// do_a_third_thing();
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// Spend(30);
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// MoveToState(next_action);
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//
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// Additional notes:
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//
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// Action and all equivalents should be negative values, since the
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// switch-for-computed-goto-for-a-coroutine structure uses __COUNTER__* for
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// its invented entry- and exit-points, meaning that negative numbers are
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// the easiest group that is safely definitely never going to collide.
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//
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// (* an extension supported by at least GCC, Clang and MSVC)
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// Spare containers:
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HalfCycles delay; // To receive any additional time added on by calls to perform_bus_operation.
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// Helper macros for common bus transactions:
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// Performs the bus operation and then applies a `Spend` of its length
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// plus any additional length returned by the bus handler.
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#define PerformBusOperation(x) \
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delay = bus_handler_.perform_bus_operation(x, is_supervisor_); \
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Spend(x.length + delay)
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// Performs no bus activity for the specified number of microcycles.
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#define IdleBus(n) \
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idle.length = HalfCycles(n * 4); \
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PerformBusOperation(idle)
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// Spin until DTACK, VPA or BERR is asserted (unless DTACK is implicit),
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// holding the bus cycle provided.
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#define WaitForDTACK(x) \
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if constexpr (!dtack_is_implicit && !dtack_ && !vpa_ && !berr_) { \
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awaiting_dtack = x; \
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awaiting_dtack.length = HalfCycles(2); \
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post_dtack_state_ = __COUNTER__+1; \
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state_ = ExecutionState::WaitForDTACK; \
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break; \
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} \
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[[fallthrough]]; case __COUNTER__:
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// Performs the bus operation provided, which will be one with a
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// SelectWord or SelectByte operation, stretching it to match the E
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// bus if VPA is currently asserted.
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//
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// TODO: If BERR is asserted, stop here and perform a bus error exception.
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//
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// TODO: If VPA is asserted, stretch this cycle.
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#define CompleteAccess(x) \
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PerformBusOperation(x)
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// Performs the memory access implied by the announce, perform pair,
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// honouring DTACK, BERR and VPA as necessary.
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#define AccessPair(val, announce, perform) \
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perform.value = &val; \
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if constexpr (!dtack_is_implicit) { \
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announce.length = HalfCycles(4); \
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} \
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PerformBusOperation(announce); \
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WaitForDTACK(announce); \
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CompleteAccess(perform);
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// Sets up the next data access size and read flags.
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#define SetupDataAccess(read_flag, select_flag) \
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access_announce.operation = Microcycle::NewAddress | Microcycle::IsData | (read_flag); \
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access.operation = access_announce.operation | (select_flag);
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// Sets the address source for the next data access.
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#define SetDataAddress(addr) \
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access.address = access_announce.address = &addr;
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// Performs the access established by SetupDataAccess into val.
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#define Access(val) \
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AccessPair(val, access_announce, access)
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// Reads the program (i.e. non-data) word from addr into val.
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#define ReadProgramWord(val) \
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AccessPair(val, read_program_announce, read_program); \
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program_counter_.l += 2;
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// Reads one futher word from the program counter and inserts it into
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// the prefetch queue.
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#define Prefetch() \
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prefetch_.high = prefetch_.low; \
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ReadProgramWord(prefetch_.low)
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using Mode = InstructionSet::M68k::AddressingMode;
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// Otherwise continue for all time, until back in debt.
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// Formatting is slightly obtuse here to make this look more like a coroutine.
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while(true) { switch(state_) {
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// Spin in place, one cycle at a time, until one of DTACK,
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// BERR or VPA is asserted.
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BeginState(WaitForDTACK):
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PerformBusOperation(awaiting_dtack);
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if(dtack_ || berr_ || vpa_) {
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state_ = post_dtack_state_;
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continue;
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}
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MoveToState(WaitForDTACK);
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// Perform the RESET exception, which seeds the stack pointer and program
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// counter, populates the prefetch queue, and then moves to instruction dispatch.
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BeginState(Reset):
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IdleBus(7); // (n-)*5 nn
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// Establish general reset state.
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status_.is_supervisor = true;
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status_.interrupt_level = 7;
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status_.trace_flag = 0;
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did_update_status();
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SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
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SetDataAddress(temporary_address_);
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temporary_address_ = 0;
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Access(registers_[15].high); // nF
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temporary_address_ += 2;
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Access(registers_[15].low); // nf
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temporary_address_ += 2;
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Access(program_counter_.high); // nV
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temporary_address_ += 2;
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Access(program_counter_.low); // nv
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Prefetch(); // np
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IdleBus(1); // n
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Prefetch(); // np
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MoveToState(Decode);
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// Inspect the prefetch queue in order to decode the next instruction,
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// and segue into the fetching of operands.
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BeginState(Decode):
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CheckOverrun();
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opcode_ = prefetch_.high.w;
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instruction_ = decoder_.decode(opcode_);
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instruction_address_ = program_counter_.l - 4;
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// TODO: check for privilege and unrecognised instructions.
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// Signal the bus handler if requested.
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if constexpr (signal_will_perform) {
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bus_handler_.will_perform(instruction_address_, opcode_);
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}
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// Ensure the first parameter is next fetched.
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next_operand_ = 0;
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// Obtain operand flags and pick a perform pattern.
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#define CASE(x) \
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case InstructionSet::M68k::Operation::x: \
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operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>();
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#define StdCASE(x, y) \
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CASE(x) \
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y; \
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\
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if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::LongWord) { \
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SetupDataAccess(Microcycle::Read, Microcycle::SelectWord); \
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MoveToState(FetchOperand_l); \
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} else { \
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if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::Byte) { \
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SetupDataAccess(Microcycle::Read, Microcycle::SelectByte); \
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} else { \
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SetupDataAccess(Microcycle::Read, Microcycle::SelectWord); \
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} \
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MoveToState(FetchOperand_bw); \
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}
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switch(instruction_.operation) {
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StdCASE(NBCD, {
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if(instruction_.mode(0) == Mode::DataRegisterDirect) {
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perform_state_ = Perform_np_n;
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} else {
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perform_state_ = Perform_np;
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}
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})
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StdCASE(SWAP, perform_state_ = Perform_np);
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StdCASE(MOVEw, perform_state_ = MOVEw);
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StdCASE(CMPb, perform_state_ = Perform_np);
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StdCASE(CMPw, perform_state_ = Perform_np);
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StdCASE(CMPl, perform_state_ = Perform_np_n);
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StdCASE(CMPAw, perform_state_ = Perform_np_n);
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StdCASE(CMPAl, perform_state_ = Perform_np_n);
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StdCASE(ANDb, perform_state_ = Perform_np);
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StdCASE(ANDw, perform_state_ = Perform_np);
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StdCASE(ANDl, {
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if(instruction_.mode(1) == Mode::DataRegisterDirect) {
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switch(instruction_.mode(0)) {
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default:
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perform_state_ = Perform_np_n;
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break;
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case Mode::DataRegisterDirect:
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case Mode::ImmediateData:
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perform_state_ = Perform_np_nn;
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break;
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}
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} else {
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perform_state_ = Perform_np;
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}
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});
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StdCASE(ORb, perform_state_ = Perform_np);
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StdCASE(ORw, perform_state_ = Perform_np);
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StdCASE(ORl, {
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if(instruction_.mode(1) == Mode::DataRegisterDirect) {
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switch(instruction_.mode(0)) {
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default:
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perform_state_ = Perform_np_n;
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break;
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case Mode::DataRegisterDirect:
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case Mode::ImmediateData:
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perform_state_ = Perform_np_nn;
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break;
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}
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} else {
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perform_state_ = Perform_np;
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}
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});
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StdCASE(EORb, perform_state_ = Perform_np);
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StdCASE(EORw, perform_state_ = Perform_np);
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StdCASE(EORl, {
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if(instruction_.mode(1) == Mode::DataRegisterDirect) {
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perform_state_ = Perform_np_nn;
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} else {
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perform_state_ = Perform_np;
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}
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})
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default:
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assert(false);
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}
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#undef CASE
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// MARK: - Fetch, dispatch.
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#define MoveToNextOperand(x) \
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++next_operand_; \
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if(next_operand_ == 2) { \
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state_ = perform_state_; \
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continue; \
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} \
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MoveToState(x)
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// Check the operand flags to determine whether the byte or word
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// operand at index next_operand_ needs to be fetched, and if so
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// then calculate the EA and do so.
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BeginState(FetchOperand_bw):
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// Check that this operand is meant to be fetched; if not then either:
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//
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// (i) this operand isn't used; or
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// (ii) its address calculation will end up conflated with performance,
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// so there's no generic bus-accurate approach.
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if(!(operand_flags_ & (1 << next_operand_))) {
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state_ = perform_state_;
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continue;
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}
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// Figure out how to fetch it.
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switch(instruction_.mode(next_operand_)) {
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case Mode::AddressRegisterDirect:
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case Mode::DataRegisterDirect:
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operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
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MoveToNextOperand(FetchOperand_bw);
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case Mode::Quick:
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operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
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MoveToNextOperand(FetchOperand_bw);
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case Mode::AddressRegisterIndirect:
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MoveToState(FetchAddressRegisterIndirect_bw);
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case Mode::AddressRegisterIndirectWithPostincrement:
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MoveToState(FetchAddressRegisterIndirectWithPostincrement_bw);
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case Mode::AddressRegisterIndirectWithPredecrement:
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MoveToState(FetchAddressRegisterIndirectWithPredecrement_bw);
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case Mode::AddressRegisterIndirectWithDisplacement:
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MoveToState(FetchAddressRegisterIndirectWithDisplacement_bw);
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case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
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MoveToState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw);
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case Mode::ProgramCounterIndirectWithDisplacement:
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MoveToState(FetchProgramCounterIndirectWithDisplacement_bw);
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case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
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MoveToState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw);
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case Mode::AbsoluteShort:
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MoveToState(FetchAbsoluteShort_bw);
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case Mode::AbsoluteLong:
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MoveToState(FetchAbsoluteLong_bw);
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case Mode::ImmediateData:
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MoveToState(FetchImmediateData_bw);
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// Should be impossible to reach.
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default:
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assert(false);
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}
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break;
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// As above, but for .l.
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BeginState(FetchOperand_l):
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if(!(operand_flags_ & (1 << next_operand_))) {
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state_ = perform_state_;
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continue;
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}
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switch(instruction_.mode(next_operand_)) {
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case Mode::AddressRegisterDirect:
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case Mode::DataRegisterDirect:
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operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
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MoveToNextOperand(FetchOperand_bw);
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case Mode::Quick:
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operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
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MoveToNextOperand(FetchOperand_bw);
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case Mode::AddressRegisterIndirect:
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MoveToState(FetchAddressRegisterIndirect_l);
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case Mode::AddressRegisterIndirectWithPostincrement:
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MoveToState(FetchAddressRegisterIndirectWithPostincrement_l);
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case Mode::AddressRegisterIndirectWithPredecrement:
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MoveToState(FetchAddressRegisterIndirectWithPredecrement_l);
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case Mode::AddressRegisterIndirectWithDisplacement:
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MoveToState(FetchAddressRegisterIndirectWithDisplacement_l);
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case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
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MoveToState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l);
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case Mode::ProgramCounterIndirectWithDisplacement:
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MoveToState(FetchProgramCounterIndirectWithDisplacement_l);
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case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
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MoveToState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l);
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case Mode::AbsoluteShort:
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MoveToState(FetchAbsoluteShort_l);
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case Mode::AbsoluteLong:
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MoveToState(FetchAbsoluteLong_l);
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case Mode::ImmediateData:
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MoveToState(FetchImmediateData_l);
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// Should be impossible to reach.
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default:
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assert(false);
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}
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break;
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// MARK: - Fetch, addressing modes.
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//
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// AddressRegisterIndirect
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//
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BeginState(FetchAddressRegisterIndirect_bw):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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SetDataAddress(effective_address_[next_operand_]);
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchAddressRegisterIndirect_l):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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SetDataAddress(effective_address_[next_operand_]);
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Access(operand_[next_operand_].high); // nR
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effective_address_[next_operand_] += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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//
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// AddressRegisterIndirectWithPostincrement
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//
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BeginState(FetchAddressRegisterIndirectWithPostincrement_bw):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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registers_[8 + instruction_.reg(next_operand_)].l +=
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byte_word_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
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SetDataAddress(effective_address_[next_operand_]);
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Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithPostincrement_l):
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
registers_[8 + instruction_.reg(next_operand_)].l += 4;
|
|
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
Access(operand_[next_operand_].high); // nR
|
|
effective_address_[next_operand_] += 2;
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
//
|
|
// AddressRegisterIndirectWithPredecrement
|
|
//
|
|
BeginState(FetchAddressRegisterIndirectWithPredecrement_bw):
|
|
registers_[8 + instruction_.reg(next_operand_)].l -=
|
|
byte_word_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
IdleBus(1); // n
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithPredecrement_l):
|
|
registers_[8 + instruction_.reg(next_operand_)].l -= 4;
|
|
effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
IdleBus(1); // n
|
|
Access(operand_[next_operand_].high); // nR
|
|
effective_address_[next_operand_] += 2;
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
//
|
|
// AddressRegisterIndirectWithDisplacement
|
|
//
|
|
BeginState(FetchAddressRegisterIndirectWithDisplacement_bw):
|
|
effective_address_[next_operand_] =
|
|
registers_[8 + instruction_.reg(next_operand_)].l +
|
|
int16_t(prefetch_.w);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithDisplacement_l):
|
|
effective_address_[next_operand_] =
|
|
registers_[8 + instruction_.reg(next_operand_)].l +
|
|
int16_t(prefetch_.w);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].high); // nR
|
|
effective_address_[next_operand_] += 2;
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
//
|
|
// ProgramCounterIndirectWithDisplacement
|
|
//
|
|
BeginState(FetchProgramCounterIndirectWithDisplacement_bw):
|
|
effective_address_[next_operand_] =
|
|
instruction_address_ + 2 +
|
|
int16_t(prefetch_.w);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchProgramCounterIndirectWithDisplacement_l):
|
|
effective_address_[next_operand_] =
|
|
instruction_address_ + 2 +
|
|
int16_t(prefetch_.w);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].high); // nR
|
|
effective_address_[next_operand_] += 2;
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
#define d8Xn(base) \
|
|
base + \
|
|
((prefetch_.w & 0x800) ? \
|
|
registers_[prefetch_.w >> 12].l : \
|
|
int16_t(registers_[prefetch_.w >> 12].w)) + \
|
|
int8_t(prefetch_.b);
|
|
|
|
//
|
|
// AddressRegisterIndirectWithIndex8bitDisplacement
|
|
//
|
|
BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw):
|
|
effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
IdleBus(1); // n
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l):
|
|
effective_address_[next_operand_] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
IdleBus(1); // n
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].high); // nR
|
|
effective_address_[next_operand_] += 2;
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
//
|
|
// ProgramCounterIndirectWithIndex8bitDisplacement
|
|
//
|
|
BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw):
|
|
effective_address_[next_operand_] = d8Xn(instruction_address_ + 2);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
IdleBus(1); // n
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l):
|
|
effective_address_[next_operand_] = d8Xn(instruction_address_ + 2);;
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
IdleBus(1); // n
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].high); // nR
|
|
effective_address_[next_operand_] += 2;
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
#undef d8Xn
|
|
|
|
//
|
|
// AbsoluteShort
|
|
//
|
|
BeginState(FetchAbsoluteShort_bw):
|
|
effective_address_[next_operand_] = int16_t(prefetch_.w);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchAbsoluteShort_l):
|
|
effective_address_[next_operand_] = int16_t(prefetch_.w);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].high); // nR
|
|
effective_address_[next_operand_] += 2;
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
//
|
|
// AbsoluteLong
|
|
//
|
|
BeginState(FetchAbsoluteLong_bw):
|
|
Prefetch(); // np
|
|
|
|
effective_address_[next_operand_] = prefetch_.l;
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchAbsoluteLong_l):
|
|
Prefetch(); // np
|
|
|
|
effective_address_[next_operand_] = prefetch_.l;
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
|
|
Prefetch(); // np
|
|
Access(operand_[next_operand_].high); // nR
|
|
effective_address_[next_operand_] += 2;
|
|
Access(operand_[next_operand_].low); // nr
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
//
|
|
// ImmediateData
|
|
//
|
|
BeginState(FetchImmediateData_bw):
|
|
operand_[next_operand_].w = prefetch_.w;
|
|
Prefetch(); // np
|
|
MoveToNextOperand(FetchOperand_bw);
|
|
|
|
BeginState(FetchImmediateData_l):
|
|
Prefetch(); // np
|
|
operand_[next_operand_].l = prefetch_.l;
|
|
Prefetch(); // np
|
|
MoveToNextOperand(FetchOperand_l);
|
|
|
|
// MARK: - Store.
|
|
|
|
// Store operand is a lot simpler: only one operand is ever stored, and its address
|
|
// is already known. So this can either skip straight back to ::Decode if the target
|
|
// is a register, otherwise a single write operation can occur.
|
|
BeginState(StoreOperand):
|
|
if(instruction_.mode(next_operand_) <= Mode::AddressRegisterDirect) {
|
|
registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_];
|
|
MoveToState(Decode);
|
|
}
|
|
|
|
if(instruction_.operand_size() == InstructionSet::M68k::DataSize::LongWord) {
|
|
MoveToState(StoreOperand_l);
|
|
}
|
|
|
|
SetupDataAccess(
|
|
0,
|
|
(instruction_.operand_size() == InstructionSet::M68k::DataSize::Byte) ? Microcycle::SelectByte : Microcycle::SelectWord);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
Access(operand_[next_operand_].low); // nw
|
|
MoveToState(Decode);
|
|
|
|
BeginState(StoreOperand_l):
|
|
SetupDataAccess(0, Microcycle::SelectWord);
|
|
SetDataAddress(effective_address_[next_operand_]);
|
|
Access(operand_[next_operand_].low); // nw
|
|
|
|
effective_address_[next_operand_] -= 2;
|
|
Access(operand_[next_operand_].high); // nW
|
|
MoveToState(Decode);
|
|
|
|
//
|
|
// Various generic forms of perform.
|
|
//
|
|
#define MoveToWritePhase() \
|
|
next_operand_ = operand_flags_ >> 3; \
|
|
if(operand_flags_ & 0x0c) MoveToState(StoreOperand) else MoveToState(Decode)
|
|
|
|
BeginState(Perform_np):
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
Prefetch(); // np
|
|
MoveToWritePhase();
|
|
|
|
BeginState(Perform_np_n):
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
Prefetch(); // np
|
|
IdleBus(1); // n
|
|
MoveToWritePhase();
|
|
|
|
BeginState(Perform_np_nn):
|
|
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
|
|
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
|
|
Prefetch(); // np
|
|
IdleBus(2); // nn
|
|
MoveToWritePhase();
|
|
|
|
#undef MoveToWritePhase
|
|
|
|
|
|
//
|
|
// Specific forms of perform.
|
|
//
|
|
|
|
BeginState(MOVEw):
|
|
switch(instruction_.mode(1)) {
|
|
case Mode::DataRegisterDirect:
|
|
case Mode::AddressRegisterDirect:
|
|
MoveToState(MOVEwRegisterDirect);
|
|
|
|
case Mode::AddressRegisterIndirectWithPostincrement:
|
|
MoveToState(MOVEwAddressRegisterIndirectWithPostincrement);
|
|
|
|
default: assert(false);
|
|
}
|
|
|
|
|
|
BeginState(MOVEwRegisterDirect):
|
|
registers_[instruction_.lreg(1)].w = operand_[1].w;
|
|
Prefetch(); // np
|
|
MoveToState(Decode);
|
|
|
|
BeginState(MOVEwAddressRegisterIndirectWithPostincrement):
|
|
// TODO: nw
|
|
assert(false);
|
|
Prefetch() // np
|
|
MoveToState(Decode);
|
|
|
|
// Various states TODO.
|
|
#define TODOState(x) \
|
|
BeginState(x): [[fallthrough]];
|
|
|
|
// TODOState(FetchImmediateData_l);
|
|
|
|
#undef TODOState
|
|
|
|
default:
|
|
printf("Unhandled state: %d; opcode is %04x\n", state_, opcode_);
|
|
assert(false);
|
|
}}
|
|
|
|
#undef Prefetch
|
|
#undef ReadProgramWord
|
|
#undef ReadDataWord
|
|
#undef AccessPair
|
|
#undef CompleteAccess
|
|
#undef WaitForDTACK
|
|
#undef IdleBus
|
|
#undef PerformBusOperation
|
|
#undef MoveToState
|
|
#undef CheckOverrun
|
|
#undef Spend
|
|
#undef ConsiderExit
|
|
|
|
}
|
|
|
|
// MARK: - Flow Controller.
|
|
|
|
void ProcessorBase::did_update_status() {
|
|
// Shuffle the stack pointers.
|
|
stack_pointers_[is_supervisor_] = registers_[15];
|
|
registers_[15] = stack_pointers_[int(status_.is_supervisor)];
|
|
is_supervisor_ = int(status_.is_supervisor);
|
|
}
|
|
|
|
// MARK: - External state.
|
|
|
|
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
|
|
CPU::MC68000Mk2::State Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::get_state() {
|
|
CPU::MC68000Mk2::State state;
|
|
|
|
// This isn't true, but will ensure that both stack_pointers_ have their proper values.
|
|
did_update_status();
|
|
|
|
for(int c = 0; c < 7; c++) {
|
|
state.registers.data[c] = registers_[c].l;
|
|
state.registers.address[c] = registers_[c + 8].l;
|
|
}
|
|
state.registers.data[7] = registers_[7].l;
|
|
|
|
state.registers.program_counter = program_counter_.l;
|
|
state.registers.status = status_.status();
|
|
state.registers.user_stack_pointer = stack_pointers_[0].l;
|
|
state.registers.supervisor_stack_pointer = stack_pointers_[1].l;
|
|
|
|
return state;
|
|
}
|
|
|
|
template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
|
|
void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::set_state(const CPU::MC68000Mk2::State &state) {
|
|
// Copy registers and the program counter.
|
|
for(int c = 0; c < 7; c++) {
|
|
registers_[c].l = state.registers.data[c];
|
|
registers_[c + 8].l = state.registers.address[c];
|
|
}
|
|
registers_[7].l = state.registers.data[7];
|
|
program_counter_.l = state.registers.program_counter;
|
|
|
|
// Set status first in order to get the proper is-supervisor flag in place.
|
|
status_.set_status(state.registers.status);
|
|
|
|
// Update stack pointers, being careful to copy the right one.
|
|
stack_pointers_[0].l = state.registers.user_stack_pointer;
|
|
stack_pointers_[1].l = state.registers.supervisor_stack_pointer;
|
|
registers_[15] = stack_pointers_[is_supervisor_];
|
|
|
|
// Ensure the local is-supervisor flag is updated.
|
|
did_update_status();
|
|
}
|
|
|
|
|
|
}
|
|
}
|
|
|
|
#endif /* _8000Mk2Implementation_h */
|