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https://github.com/TomHarte/CLK.git
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Improve logging, factor out phase_matches per TODO comment.
This commit is contained in:
Thomas Harte
parent
5ed60f9153
commit
04f5d29ed9
@ -8,12 +8,18 @@
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#include "ncr5380.hpp"
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#ifndef NDEBUG
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#define NDEBUG
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#endif
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//#ifndef NDEBUG
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//#define NDEBUG
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//#endif
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#define LOG_PREFIX "[5380] "
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#include "../../Outputs/Log.hpp"
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// TODO:
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//
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// end_of_dma_ should be set if: /EOP && /DACK && (/RD || /WR); for at least 100ns.
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using namespace NCR::NCR5380;
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using SCSI::Line;
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@ -32,7 +38,7 @@ NCR5380::NCR5380(SCSI::Bus &bus, int clock_rate) :
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void NCR5380::write(int address, uint8_t value, bool) {
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switch(address & 7) {
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case 0:
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LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value));
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LOG("[0] Set current SCSI bus state to " << PADHEX(2) << int(value));
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data_bus_ = value;
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if(dma_request_ && dma_operation_ == DMAOperation::Send) {
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@ -41,7 +47,7 @@ void NCR5380::write(int address, uint8_t value, bool) {
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break;
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case 1: {
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LOG("[SCSI 1] Initiator command register set: " << PADHEX(2) << int(value));
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LOG("[1] Initiator command register set: " << PADHEX(2) << int(value));
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initiator_command_ = value;
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bus_output_ &= ~(Line::Reset | Line::Acknowledge | Line::Busy | Line::SelectTarget | Line::Attention);
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@ -57,7 +63,7 @@ void NCR5380::write(int address, uint8_t value, bool) {
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} break;
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case 2:
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LOG("[SCSI 2] Set mode: " << PADHEX(2) << int(value));
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LOG("[2] Set mode: " << PADHEX(2) << int(value));
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mode_ = value;
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// bit 7: 1 = use block mode DMA mode (if DMA mode is also enabled)
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@ -88,31 +94,36 @@ void NCR5380::write(int address, uint8_t value, bool) {
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bus_.update_observers();
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break;
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}
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// "[The End of DMA Transfer] bit is reset when the DMA MODE bit
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// is reset (0) in the Mode Register".
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end_of_dma_ &= bool(value & 0x2);
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update_control_output();
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break;
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case 3: {
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LOG("[SCSI 3] Set target command: " << PADHEX(2) << int(value));
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LOG("[3] Set target command: " << PADHEX(2) << int(value));
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target_command_ = value;
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update_control_output();
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} break;
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case 4:
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LOG("[SCSI 4] Set select enabled: " << PADHEX(2) << int(value));
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LOG("[4] Set select enabled: " << PADHEX(2) << int(value));
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break;
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case 5:
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LOG("[SCSI 5] Start DMA send: " << PADHEX(2) << int(value));
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LOG("[5] Start DMA send: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::Send;
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break;
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case 6:
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LOG("[SCSI 6] Start DMA target receive: " << PADHEX(2) << int(value));
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LOG("[6] Start DMA target receive: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::TargetReceive;
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break;
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case 7:
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LOG("[SCSI 7] Start DMA initiator receive: " << PADHEX(2) << int(value));
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LOG("[7] Start DMA initiator receive: " << PADHEX(2) << int(value));
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dma_operation_ = DMAOperation::InitiatorReceive;
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break;
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}
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@ -136,7 +147,7 @@ void NCR5380::write(int address, uint8_t value, bool) {
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uint8_t NCR5380::read(int address, bool) {
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switch(address & 7) {
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case 0:
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LOG("[SCSI 0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
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LOG("[0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
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if(dma_request_ && dma_operation_ == DMAOperation::InitiatorReceive) {
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return dma_acknowledge();
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@ -144,7 +155,7 @@ uint8_t NCR5380::read(int address, bool) {
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return uint8_t(bus_.get_state());
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case 1:
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LOG("[SCSI 1] Initiator command register get: " << (arbitration_in_progress_ ? 'p' : '-') << (lost_arbitration_ ? 'l' : '-'));
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LOG("[1] Initiator command register get: " << (arbitration_in_progress_ ? 'p' : '-') << (lost_arbitration_ ? 'l' : '-'));
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return
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// Bits repeated as they were set.
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(initiator_command_ & ~0x60) |
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@ -156,11 +167,11 @@ uint8_t NCR5380::read(int address, bool) {
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(lost_arbitration_ ? 0x20 : 0x00);
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case 2:
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LOG("[SCSI 2] Get mode");
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LOG("[2] Get mode");
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return mode_;
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case 3:
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LOG("[SCSI 3] Get target command");
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LOG("[3] Get target command");
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return target_command_;
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case 4: {
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@ -174,41 +185,37 @@ uint8_t NCR5380::read(int address, bool) {
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((bus_state & Line::Input) ? 0x04 : 0x00) |
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((bus_state & Line::SelectTarget) ? 0x02 : 0x00) |
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((bus_state & Line::Parity) ? 0x01 : 0x00);
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LOG("[SCSI 4] Get current bus state: " << PADHEX(2) << int(result));
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LOG("[4] Get current bus state: " << PADHEX(2) << int(result));
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return result;
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}
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case 5: {
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const auto bus_state = bus_.get_state();
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const bool phase_matches =
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(target_output() & (Line::Message | Line::Control | Line::Input)) ==
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(bus_state & (Line::Message | Line::Control | Line::Input));
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const uint8_t result =
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/* b7 = end of DMA */
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(end_of_dma_ ? 0x80 : 0x00) |
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((dma_request_ && state_ == ExecutionState::PerformingDMA) ? 0x40 : 0x00) |
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/* b5 = parity error */
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/* b4 = IRQ active */
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(phase_matches ? 0x08 : 0x00) |
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(phase_matches() ? 0x08 : 0x00) |
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/* b2 = busy error */
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((bus_state & Line::Attention) ? 0x02 : 0x00) |
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((bus_state & Line::Acknowledge) ? 0x01 : 0x00);
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LOG("[SCSI 5] Get bus and status: " << PADHEX(2) << int(result));
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LOG("[5] Get bus and status: " << PADHEX(2) << int(result));
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return result;
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}
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case 6:
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LOG("[SCSI 6] Get input data");
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LOG("[6] Get input data");
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return 0xff;
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case 7:
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LOG("[SCSI 7] Reset parity/interrupt");
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LOG("[7] Reset parity/interrupt");
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return 0xff;
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}
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return 0;
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}
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SCSI::BusState NCR5380::target_output() {
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SCSI::BusState NCR5380::target_output() const {
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SCSI::BusState output = SCSI::DefaultBusState;
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if(target_command_ & 0x08) output |= Line::Request;
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if(target_command_ & 0x04) output |= Line::Message;
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@ -233,6 +240,14 @@ void NCR5380::update_control_output() {
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}
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void NCR5380::scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double time_since_change) {
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/*
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When connected as an Initiator with DMA Mode True,
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if the phase lines I//O, C//D, and /MSG do not match the
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phase bits in the Target Command Register, a phase mismatch
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interrupt is generated when /REQ goes active.
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*/
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switch(state_) {
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default: break;
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@ -341,3 +356,10 @@ void NCR5380::dma_acknowledge(uint8_t value) {
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update_control_output();
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bus_.set_device_output(device_id_, bus_output_);
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}
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bool NCR5380::phase_matches() const {
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const auto bus_state = bus_.get_state();
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return
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(target_output() & (Line::Message | Line::Control | Line::Input)) ==
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(bus_state & (Line::Message | Line::Control | Line::Input));
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}
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@ -58,6 +58,7 @@ class NCR5380 final: public SCSI::Bus::Observer {
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bool assert_data_bus_ = false;
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bool dma_request_ = false;
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bool dma_acknowledge_ = false;
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bool end_of_dma_ = false;
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enum class ExecutionState {
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None,
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@ -75,10 +76,11 @@ class NCR5380 final: public SCSI::Bus::Observer {
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void set_execution_state(ExecutionState state);
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SCSI::BusState target_output();
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SCSI::BusState target_output() const;
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void update_control_output();
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void scsi_bus_did_change(SCSI::Bus *, SCSI::BusState new_state, double time_since_change) final;
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bool phase_matches() const;
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};
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}
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