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mirror of https://github.com/TomHarte/CLK.git synced 2024-06-25 18:30:07 +00:00

Attempt to generalise moving from CPU.

This commit is contained in:
Thomas Harte 2023-03-03 21:40:48 -05:00
parent 3381e6b5aa
commit 0ea1da10d6
2 changed files with 18 additions and 17 deletions

View File

@ -921,12 +921,12 @@ void Base<personality>::commit_register(int reg, uint8_t value) {
case 0b1000: Begin(LogicalFill); break; // LMMV [logical move, VDP to VRAM, i.e. solid-colour fill].
case 0b1001: Begin(LogicalMove); break; // LMMM [logical move, VRAM to VRAM].
case 0b1010: break; // TODO: lmcm. [logical move, VRAM to CPU]
case 0b1011: Begin(LogicalMoveFromCPU); break; // LMMC [logical move, CPU to VRAM]
case 0b1011: Begin(MoveFromCPU<true>); break; // LMMC [logical move, CPU to VRAM].
case 0b1100: Begin(HighSpeedFill); break; // HMMV [high-speed move, VDP to VRAM, i.e. single-byte fill].
case 0b1101: Begin(HighSpeedMove); break; // HMMM [high-speed move, VRAM to VRAM].
case 0b1110: break; // TODO: ymmm. [high-speed move, y only, VRAM to VRAM]
case 0b1111: break; // TODO: hmmc. [high-speed move, CPU to VRAM]
case 0b1111: Begin(MoveFromCPU<false>); break; // HMMC [high-speed move, CPU to VRAM].
}
#undef Begin

View File

@ -295,29 +295,30 @@ template <bool logical, bool include_source> struct Rectangle: public Command {
// MARK: - Rectangular moves to/from CPU.
struct LogicalMoveFromCPU: public Rectangle<true, false> {
LogicalMoveFromCPU(CommandContext &context) : Rectangle(context) {
is_cpu_transfer = true;
template <bool logical> struct MoveFromCPU: public Rectangle<logical, false> {
MoveFromCPU(CommandContext &context) : Rectangle<logical, false>(context) {
Command::is_cpu_transfer = true;
// This command is started with the first colour ready to transfer.
cycles = 32;
access = AccessType::PlotPoint;
Command::cycles = 32;
Command::access = logical ? Command::AccessType::PlotPoint : Command::AccessType::WriteByte;
}
void advance(int) final {
switch(access) {
void advance(int pixels_per_byte) final {
switch(Command::access) {
default: break;
case AccessType::WaitForColourReceipt:
cycles = 32;
access = AccessType::PlotPoint;
case Command::AccessType::WaitForColourReceipt:
Command::cycles = 32;
Command::access = logical ? Command::AccessType::PlotPoint : Command::AccessType::WriteByte;
break;
case AccessType::PlotPoint:
cycles = 0;
access = AccessType::WaitForColourReceipt;
if(advance_pixel()) {
cycles = 64;
case Command::AccessType::WriteByte:
case Command::AccessType::PlotPoint:
Command::cycles = 0;
Command::access = Command::AccessType::WaitForColourReceipt;
if(Rectangle<logical, false>::advance_pixel(pixels_per_byte)) {
Command::cycles = 64;
// TODO: I'm not sure this will be honoured per the outer wrapping.
}
break;