mirror of
https://github.com/TomHarte/CLK.git
synced 2025-04-07 01:38:25 +00:00
Expanded a little on operations, added an implementation or two.
This commit is contained in:
Thomas Harte
parent
58efca835f
commit
11d05fb3b8
@ -17,7 +17,6 @@
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4B14145E1B5887AA00E04248 /* 6502AllRAM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B1414591B58879D00E04248 /* 6502AllRAM.cpp */; };
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4B1414601B58885000E04248 /* WolfgangLorenzTests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4B14145F1B58885000E04248 /* WolfgangLorenzTests.swift */; };
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4B1414621B58888700E04248 /* KlausDormannTests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4B1414611B58888700E04248 /* KlausDormannTests.swift */; };
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4B1482391ECE94F30099EA63 /* Z80AllRAM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA11D1ECBD9BD00AC40C1 /* Z80AllRAM.cpp */; };
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4B1D08061E0F7A1100763741 /* TimeTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B1D08051E0F7A1100763741 /* TimeTests.mm */; };
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4B1E85751D170228001EF87D /* Typer.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B1E85731D170228001EF87D /* Typer.cpp */; };
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4B1E85811D176468001EF87D /* 6532Tests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4B1E85801D176468001EF87D /* 6532Tests.swift */; };
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@ -2504,7 +2503,6 @@
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4BF8295D1D8F048B001BAE39 /* MFM.cpp in Sources */,
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4BE77A2E1D84ADFB00BC3827 /* File.cpp in Sources */,
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4B5FADBD1DE31D1500AEC565 /* OricMFMDSK.cpp in Sources */,
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4B1482391ECE94F30099EA63 /* Z80AllRAM.cpp in Sources */,
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4B77069D1EC904570053B588 /* Z80.cpp in Sources */,
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4BAB62B51D327F7E00DF5BA0 /* G64.cpp in Sources */,
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4BD468F71D8DF41D0084958B /* 1770.cpp in Sources */,
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@ -84,8 +84,9 @@ struct MicroOp {
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MoveToNextProgram,
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Increment16,
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Decrement16,
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Move8,
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Move16,
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Jump,
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None
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} type;
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@ -121,24 +122,78 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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void decode_base_operation(uint8_t operation) {
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#define XX {MicroOp::None, 0}
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#define FETCH(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}
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#define FETCH16(x, y) FETCH(x.bytes.low, y), {MicroOp::Increment16, &y.full}, FETCH(x.bytes.high, y), {MicroOp::Increment16, &y.full}
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#define FETCH16L(x, y) FETCH(x.bytes.low, y), {MicroOp::Increment16, &y.full}, FETCH(x.bytes.high, y)
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#define FETCH_LOW() FETCH(address_.bytes.low, pc_)
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#define FETCH_HIGH() FETCH(address_.bytes.high, pc_)
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#define FETCH(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}, {MicroOp::Increment16, &y.full}
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#define FETCHL(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}
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#define STOREL(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Write, 3, &y.full, &x}}
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#define FETCH16(x, y) FETCH(x.bytes.low, y), FETCH(x.bytes.high, y)
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#define FETCH16L(x, y) FETCH(x.bytes.low, y), FETCHL(x.bytes.high, y)
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#define PUSH(x) STOREL(x.bytes.high, sp_), {MicroOp::Decrement16, &sp_.full}, STOREL(x.bytes.low, sp_), {MicroOp::Decrement16, &sp_.full}
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#define WAIT(n) {MicroOp::BusOperation, nullptr, nullptr, {Internal, n} }
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#define Program(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
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static const MicroOp base_program_table[256][10] = {
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x00
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x08
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x10
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x18
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x20
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XX, XX, // 0x28
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static const MicroOp base_program_table[256][20] = {
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{ {MicroOp::MoveToNextProgram} }, /* 0x00 NOP */
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Program(FETCH16(bc_, pc_)), /* 0x01 LD BC, nn */
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XX, /* 0x02 LD (BC), A */
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XX, /* 0x03 INC BC */
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XX, /* 0x04 INC B */
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XX, /* 0x05 DEC B */
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Program(FETCH(bc_.bytes.high, pc_)), /* 0x06 LD B, n */
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XX, /* 0x07 RLCA */
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XX, /* 0x08 EX AF, AF' */
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XX, /* 0x09 ADD HL, BC */
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XX, /* 0x0a LD A, (BC) */
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XX, /* 0x0b DEC BC */
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XX, /* 0x0c INC C */
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XX, /* 0x0d DEC C */
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Program(FETCH(bc_.bytes.low, pc_)), /* 0x0e LD C, n */
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XX, /* 0x0f RRCA */
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XX, /* 0x10 DJNZ */
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Program(FETCH16(de_, pc_)), /* 0x11 LD DE, nn */
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XX, /* 0x12 LD (DE), A */
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XX, /* 0x13 INC DE */
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XX, /* 0x14 INC D */
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XX, /* 0x15 DEC D */
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Program(FETCH(de_.bytes.high, pc_)), /* 0x16 LD D, n */
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XX, /* 0x17 RLA */
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XX, /* 0x18 JR */
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XX, /* 0x19 ADD HL, DE */
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XX, /* 0x1a LD A, (DE) */
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XX, /* 0x1b DEC DE */
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XX, /* 0x1c INC E */
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XX, /* 0x1d DEC E */
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Program(FETCH(de_.bytes.low, pc_)), /* 0x1e LD E, n */
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XX, /* 0x1f RRA */
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XX, /* 0x20 JR NZ */
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Program(FETCH16(hl_, pc_)), /* 0x21 LD HL, nn */
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XX, /* 0x22 LD (nn), HL */
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XX, /* 0x23 INC HL */
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XX, /* 0x24 INC H */
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XX, /* 0x25 DEC H */
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Program(FETCH(hl_.bytes.high, pc_)), /* 0x26 LD H, n */
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XX, /* 0x27 DAA */
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XX, /* 0x28 JR Z */
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XX, /* 0x29 ADD HL, HL */
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Program(FETCH16(address_, pc_), FETCH16L(hl_, address_)), /* 0x2a LD HL, (nn) */
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XX, XX, XX, XX, XX,
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x30
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XX, /* 0x2b DEC HL */
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XX, /* 0x2c INC L */
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XX, /* 0x2d DEC L */
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Program(FETCH(hl_.bytes.low, pc_)), /* 0x2e LD L, n */
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XX, /* 0x2f CPL */
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XX, /* 0x30 JR NC */
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Program(FETCH16(sp_, pc_)), /* 0x31 LD SP, nn */
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XX, /* 0x32 LD (nn), A */
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XX, /* 0x33 INC SP */
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XX, /* 0x34 INC (HL) */
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XX, /* 0x35 DEC (HL) */
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XX, /* 0x36 LD (HL), n */
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XX, /* 0x37 SCF */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x38
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x40
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XX, XX, XX, XX, XX, XX, XX, XX, // 0x48
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@ -156,15 +211,22 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xa8
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xb0
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xb8
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XX, /* 0xc0 */
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XX, /* 0xc1 */
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XX, /* 0xc2 */
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Program(FETCH16L(address_, pc_), {MicroOp::Jump}), /* 0xc3 JP nn */
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XX, /* 0xc4 */
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XX, /* 0xc5 */
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XX, /* 0xc6 */
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XX, /* 0xc7 */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xc8
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XX, /* 0xc0 RET NZ */
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XX, /* 0xc1 POP BC */
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XX, /* 0xc2 JP NZ */
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Program(FETCH16L(address_, pc_), {MicroOp::Move16, &address_.full, &pc_.full}), /* 0xc3 JP nn */
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XX, /* 0xc4 CALL NZ */
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XX, /* 0xc5 PUSH BC */
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XX, /* 0xc6 ADD A, n */
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XX, /* 0xc7 RST 00h */
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XX, /* 0xc8 RET Z */
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XX, /* 0xc9 RET */
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XX, /* 0xca JP Z */
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XX, /* 0xcb [CB page] */
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XX, /* 0xcc CALL Z */
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Program(FETCH16(address_, pc_), WAIT(1), PUSH(pc_), {MicroOp::Move16, &address_.full, &pc_.full}), /* 0xcd CALL */
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XX, /* 0xce ADC A, n */
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XX, /* 0xcf RST 08h */
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xd0
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xd8
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XX, XX, XX, XX, XX, XX, XX, XX, // 0xe0
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@ -197,7 +259,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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*/
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void run_for_cycles(int number_of_cycles) {
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static const MicroOp fetch_decode_execute[] = {
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{ MicroOp::BusOperation, 4, nullptr, nullptr, {ReadOpcode, &pc_.full, &operation_}},
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{ MicroOp::BusOperation, nullptr, nullptr, {ReadOpcode, 4, &pc_.full, &operation_}},
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{ MicroOp::DecodeOperation },
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{ MicroOp::MoveToNextProgram }
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};
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@ -230,10 +292,10 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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decode_base_operation(operation_);
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break;
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case MicroOp::Increment16: (*((uint16_t *)operation->source))++; break;
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case MicroOp::Jump: pc_ = address_; break;
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case MicroOp::Move16: *(uint16_t *)operation->destination = *(uint16_t *)operation->source; break;
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case MicroOp::Increment16: (*(uint16_t *)operation->source)++; break;
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case MicroOp::Decrement16: (*(uint16_t *)operation->source)--; break;
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case MicroOp::Move8: *(uint8_t *)operation->destination = *(uint8_t *)operation->source; break;
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case MicroOp::Move16: *(uint16_t *)operation->destination = *(uint16_t *)operation->source; break;
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default:
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printf("Unhandled Z80 operation %d\n", operation->type);
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@ -21,9 +21,13 @@ int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) {
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*cycle->value = memory_[*cycle->address];
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break;
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case BusOperation::Write:
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printf("w %04x\n", *cycle->address);
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memory_[*cycle->address] = *cycle->value;
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break;
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case BusOperation::Internal:
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break;
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default:
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printf("???\n");
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break;
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