6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 08:49:37 +00:00
Code Issues Projects Releases Wiki Activity

Convert vram_access_delay into a free-standing function.

Browse Source
This commit is contained in:
Thomas Harte 2023-01-01 13:51:29 -05:00
parent 11542e7a7f
commit 180045ada6
2 changed files with 12 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Components/9918/9918.cpp
View File

@ -86,6 +86,16 @@ struct ReverseTable {
constexpr ReverseTable reverse_table; constexpr ReverseTable reverse_table;
template <Personality personality> constexpr int vram_access_delay() {
// This seems to be correct for all currently-modelled VDPs;
// it's the delay between an external device scheduling a
// read or write and the very first time that can occur
// (though, in practice, it won't happen until the next
// external slot after this number of cycles after the
// device has requested the read or write).
return 6;
}
} }
template <Personality personality> template <Personality personality>
@ -549,7 +559,7 @@ void TMS9918<personality>::write(int address, uint8_t value) {
// Enqueue the write to occur at the next available slot. // Enqueue the write to occur at the next available slot.
this->read_ahead_buffer_ = value; this->read_ahead_buffer_ = value;
this->queued_access_ = MemoryAccess::Write; this->queued_access_ = MemoryAccess::Write;
this->cycles_until_access_ = this->vram_access_delay(); this->cycles_until_access_ = vram_access_delay<personality>();
return; return;
} }
@ -664,7 +674,7 @@ void TMS9918<personality>::write(int address, uint8_t value) {
// A read request is enqueued upon setting the address; conversely a write // A read request is enqueued upon setting the address; conversely a write
// won't be enqueued unless and until some actual data is supplied. // won't be enqueued unless and until some actual data is supplied.
this->queued_access_ = MemoryAccess::Read; this->queued_access_ = MemoryAccess::Read;
this->cycles_until_access_ = this->vram_access_delay(); this->cycles_until_access_ = vram_access_delay<personality>();
} }
this->master_system_.cram_is_selected = false; this->master_system_.cram_is_selected = false;
} }

9
Components/9918/Implementation/9918Base.hpp
View File

@ -172,15 +172,6 @@ template <Personality personality> struct Base {
MemoryAccess queued_access_ = MemoryAccess::None; MemoryAccess queued_access_ = MemoryAccess::None;
int cycles_until_access_ = 0; int cycles_until_access_ = 0;
int minimum_access_column_ = 0; int minimum_access_column_ = 0;
int vram_access_delay() {
// This seems to be correct for all currently-modelled VDPs;
// it's the delay between an external device scheduling a
// read or write and the very first time that can occur
// (though, in practice, it won't happen until the next
// external slot after this number of cycles after the
// device has requested the read or write).
return 6;
}
// Holds the main status register. // Holds the main status register.
uint8_t status_ = 0; uint8_t status_ = 0;