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Convert vram_access_delay
into a free-standing function.
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parent
11542e7a7f
commit
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@ -86,6 +86,16 @@ struct ReverseTable {
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constexpr ReverseTable reverse_table;
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template <Personality personality> constexpr int vram_access_delay() {
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// This seems to be correct for all currently-modelled VDPs;
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// it's the delay between an external device scheduling a
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// read or write and the very first time that can occur
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// (though, in practice, it won't happen until the next
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// external slot after this number of cycles after the
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// device has requested the read or write).
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return 6;
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}
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}
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template <Personality personality>
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@ -549,7 +559,7 @@ void TMS9918<personality>::write(int address, uint8_t value) {
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// Enqueue the write to occur at the next available slot.
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this->read_ahead_buffer_ = value;
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this->queued_access_ = MemoryAccess::Write;
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this->cycles_until_access_ = this->vram_access_delay();
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this->cycles_until_access_ = vram_access_delay<personality>();
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return;
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}
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@ -664,7 +674,7 @@ void TMS9918<personality>::write(int address, uint8_t value) {
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// A read request is enqueued upon setting the address; conversely a write
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// won't be enqueued unless and until some actual data is supplied.
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this->queued_access_ = MemoryAccess::Read;
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this->cycles_until_access_ = this->vram_access_delay();
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this->cycles_until_access_ = vram_access_delay<personality>();
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}
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this->master_system_.cram_is_selected = false;
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}
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@ -172,15 +172,6 @@ template <Personality personality> struct Base {
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MemoryAccess queued_access_ = MemoryAccess::None;
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int cycles_until_access_ = 0;
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int minimum_access_column_ = 0;
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int vram_access_delay() {
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// This seems to be correct for all currently-modelled VDPs;
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// it's the delay between an external device scheduling a
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// read or write and the very first time that can occur
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// (though, in practice, it won't happen until the next
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// external slot after this number of cycles after the
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// device has requested the read or write).
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return 6;
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}
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// Holds the main status register.
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uint8_t status_ = 0;
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