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https://github.com/TomHarte/CLK.git
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Switch — messily — to a more compact way of indicating sequence.
This commit is contained in:
Thomas Harte
parent
17a2ce0464
commit
1bb809098c
@ -250,56 +250,37 @@ void Executor<model, BusHandler>::run_for_instructions(int count) {
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// Obtain the appropriate sequence.
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//
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// TODO: make a decision about whether this goes into a fully-decoded Instruction.
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Sequence<model> sequence(instruction.operation);
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const auto flags = operand_flags<model>(instruction.operation);
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// Perform it.
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while(!sequence.empty()) {
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const auto step = sequence.pop_front();
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// TODO: potential alignment exception, here and in store.
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#define fetch_operand(n) \
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if(effective_address_[n].requires_fetch) { \
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read(instruction.size(), effective_address_[n].value.l, operand_[n]); \
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}
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switch(step) {
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default: assert(false); // i.e. TODO
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if(flags & FetchOp1) { fetch_operand(0); }
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if(flags & FetchOp2) { fetch_operand(1); }
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case Step::FetchOp1:
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case Step::FetchOp2: {
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const auto index = int(step) & 1;
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#undef fetch_operand
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// If the operand wasn't indirect, it's already fetched.
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if(!effective_address_[index].requires_fetch) continue;
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perform<model>(instruction, operand_[0], operand_[1], status_, *this);
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// TODO: potential bus alignment exception.
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read(instruction.size(), effective_address_[index].value.l, operand_[index]);
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} break;
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// TODO: is it worth holding registers as a single block to avoid conditional below?
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#define store_operand(n) \
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if(!effective_address_[n].requires_fetch) { \
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if(instruction.mode(n) == AddressingMode::DataRegisterDirect) { \
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data_[instruction.reg(n)] = operand_[n]; \
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} else { \
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address_[instruction.reg(n)] = operand_[n]; \
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} \
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} else { \
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write(instruction.size(), effective_address_[n].value.l, operand_[n]); \
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}
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case Step::Perform:
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perform<model>(instruction, operand_[0], operand_[1], status_, *this);
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break;
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if(flags & StoreOp1) { store_operand(0); }
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if(flags & StoreOp2) { store_operand(1); }
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case Step::StoreOp1:
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case Step::StoreOp2: {
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const auto index = int(step) & 1;
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// If the operand wasn't indirect, store directly to Dn or An.
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if(!effective_address_[index].requires_fetch) {
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// This must be either address or data register indirect.
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assert(
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instruction.mode(index) == AddressingMode::DataRegisterDirect ||
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instruction.mode(index) == AddressingMode::AddressRegisterDirect);
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// TODO: is it worth holding registers as a single block to avoid this conditional?
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if(instruction.mode(index) == AddressingMode::DataRegisterDirect) {
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data_[instruction.reg(index)] = operand_[index];
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} else {
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address_[instruction.reg(index)] = operand_[index];
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}
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break;
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}
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// TODO: potential bus alignment exception.
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write(instruction.size(), effective_address_[index].value.l, operand_[index]);
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} break;
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}
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}
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#undef store_operand
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}
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}
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@ -12,6 +12,7 @@
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using namespace InstructionSet::M68k;
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/*
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template <Step... T> struct Steps {
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static constexpr uint32_t value = 0;
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};
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@ -110,3 +111,4 @@ template class InstructionSet::M68k::Sequence<Model::M68010>;
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template class InstructionSet::M68k::Sequence<Model::M68020>;
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template class InstructionSet::M68k::Sequence<Model::M68030>;
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template class InstructionSet::M68k::Sequence<Model::M68040>;
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*/
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@ -12,64 +12,93 @@
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#include "Instruction.hpp"
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#include "Model.hpp"
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#include <cassert>
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namespace InstructionSet {
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namespace M68k {
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/// Additional guarantees: [Fetch/Store][1/2] have an LSB of 0 for
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/// operand 1, and an LSB of 1 for operand 2.
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enum class Step {
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/// No further steps remain.
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Done,
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/// Do the logical operation.
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Perform,
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/// Fetch the value of operand 1.
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FetchOp1,
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/// Fetch the value of operand 2.
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FetchOp2,
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/// Store the value of operand 1.
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StoreOp1,
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/// Store the value of operand 2.
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StoreOp2,
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/// A catch-all for bus activity that doesn't fit the pattern
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/// of fetch/stop operand 1/2, e.g. this opaquely covers almost
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/// the entirety of MOVEM.
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///
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/// TODO: list all operations that contain this step,
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/// and to cover what activity.
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SpecificBusActivity,
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static constexpr uint8_t FetchOp1 = (1 << 0);
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static constexpr uint8_t FetchOp2 = (1 << 1);
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static constexpr uint8_t StoreOp1 = (1 << 2);
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static constexpr uint8_t StoreOp2 = (1 << 3);
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Max = SpecificBusActivity
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};
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/*!
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Provides a bitfield with a value in the range 0–15 indicating which of the provided operation's
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operands are accessed via standard fetch and store cycles.
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/// Indicates the abstract steps necessary to perform an operation,
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/// at least as far as that's generic.
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template<Model model> class Sequence {
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public:
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Sequence(Operation);
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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*/
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template <Model model, Operation t_operation = Operation::Undefined> uint8_t operand_flags(Operation r_operation = Operation::Undefined) {
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switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
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default:
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assert(false);
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/// @returns The next @c Step to perform, or @c Done
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/// if no further steps remain. This step is removed from the
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/// list of remaining steps.
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Step pop_front() {
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static_assert(int(Step::Max) < 16);
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const auto step = Step(steps_ & 15);
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steps_ >>= 4;
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return step;
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}
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//
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// No operands are fetched or stored.
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//
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case Operation::LEA:
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case Operation::PEA:
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return 0;
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/// @returns @c true if no steps other than @c Done remain;
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/// @c false otherwise.
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bool empty() {
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return !steps_;
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}
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//
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// Single-operand read.
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//
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case Operation::MOVEtoSR: case Operation::MOVEtoCCR: case Operation::MOVEtoUSP:
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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return FetchOp1;
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private:
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uint32_t steps_ = 0;
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//
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// Single-operand write.
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//
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case Operation::MOVEfromSR: case Operation::MOVEfromUSP:
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return StoreOp1;
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uint32_t steps_for(Operation);
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};
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//
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// Single-operand read-modify-write.
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//
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case Operation::NBCD:
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case Operation::EXTbtow: case Operation::EXTwtol:
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return FetchOp1 | StoreOp1;
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//
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// Two-operand; read both.
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//
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case Operation::CMPb: case Operation::CMPw: case Operation::CMPl:
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case Operation::CMPAw: case Operation::CMPAl:
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return FetchOp1 | FetchOp2;
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//
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// Two-operand; read source, write dest.
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//
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case Operation::MOVEb: case Operation::MOVEw: case Operation::MOVEl:
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case Operation::MOVEAw: case Operation::MOVEAl:
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return FetchOp1 | StoreOp2;
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//
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// Two-operand; read both, write dest.
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//
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case Operation::ABCD: case Operation::SBCD:
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case Operation::ADDb: case Operation::ADDw: case Operation::ADDl:
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case Operation::ADDAw: case Operation::ADDAl:
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case Operation::ADDXb: case Operation::ADDXw: case Operation::ADDXl:
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case Operation::SUBb: case Operation::SUBw: case Operation::SUBl:
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case Operation::SUBAw: case Operation::SUBAl:
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case Operation::SUBXb: case Operation::SUBXw: case Operation::SUBXl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl:
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return FetchOp1 | FetchOp2 | StoreOp2;
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//
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// Two-operand; read both, write both.
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//
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case Operation::EXG:
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return FetchOp1 | FetchOp2 | StoreOp1 | StoreOp2;
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}
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}
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static_assert(sizeof(Sequence<Model::M68000>) == sizeof(uint32_t));
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}
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}
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