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https://github.com/TomHarte/CLK.git
synced 2025-02-16 18:30:32 +00:00
Use simplified control lines when appropriate.
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fd0fe66851
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@ -32,7 +32,9 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandlerT<type> {
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// Record the basics of the operation.
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auto &cycle = cycles.emplace_back();
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cycle.operation = operation;
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cycle.extended_bus = processor.get_extended_bus_output();
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if constexpr (has_extended_bus_output(type)) {
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cycle.extended_bus = processor.get_extended_bus_output();
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}
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// Perform the operation, and fill in the cycle's value.
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using BusOperation = CPU::MOS6502Esque::BusOperation;
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@ -113,7 +115,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandlerT<type> {
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CPU::MOS6502Esque::BusOperation operation;
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std::optional<AddressType> address;
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std::optional<uint8_t> value;
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int extended_bus;
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int extended_bus = 0;
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};
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std::vector<Cycle> cycles;
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@ -263,12 +265,6 @@ template <CPU::MOS6502Esque::Type type> void generate() {
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assert(false);
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}
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using ExtendedBusOutput = CPU::WDC65816::ExtendedBusOutput;
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const bool emulation = cycle.extended_bus & ExtendedBusOutput::Emulation;
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const bool memory_size = cycle.extended_bus & ExtendedBusOutput::MemorySize;
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const bool index_size = cycle.extended_bus & ExtendedBusOutput::IndexSize;
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const bool memory_lock = cycle.extended_bus & ExtendedBusOutput::MemoryLock;
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fprintf(target, "[");
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if(cycle.address) {
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fprintf(target, "%d, ", *cycle.address);
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@ -280,16 +276,31 @@ template <CPU::MOS6502Esque::Type type> void generate() {
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} else {
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fprintf(target, "null, ");
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}
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fprintf(target, "\"%c%c%c%c%c%c%c%c\"]",
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vda ? 'd' : '-',
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vpa ? 'p' : '-',
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vpb ? 'v' : '-',
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wait ? '-' : (read ? 'r' : 'w'),
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wait ? '-' : (emulation ? 'e' : '-'),
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wait ? '-' : (memory_size ? 'm' : '-'),
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wait ? '-' : (index_size ? 'x' : '-'),
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wait ? '-' : (memory_lock ? 'l' : '-')
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);
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if(has_emulation) {
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using ExtendedBusOutput = CPU::WDC65816::ExtendedBusOutput;
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const bool emulation = cycle.extended_bus & ExtendedBusOutput::Emulation;
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const bool memory_size = cycle.extended_bus & ExtendedBusOutput::MemorySize;
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const bool index_size = cycle.extended_bus & ExtendedBusOutput::IndexSize;
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const bool memory_lock = cycle.extended_bus & ExtendedBusOutput::MemoryLock;
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fprintf(target, "\"%c%c%c%c%c%c%c%c\"]",
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vda ? 'd' : '-',
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vpa ? 'p' : '-',
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vpb ? 'v' : '-',
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wait ? '-' : (read ? 'r' : 'w'),
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wait ? '-' : (emulation ? 'e' : '-'),
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wait ? '-' : (memory_size ? 'm' : '-'),
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wait ? '-' : (index_size ? 'x' : '-'),
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wait ? '-' : (memory_lock ? 'l' : '-')
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);
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} else {
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if(read) {
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fprintf(target, "\"read\"]");
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} else {
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fprintf(target, "\"write\"]");
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}
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}
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}
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// Terminate object.
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@ -68,6 +68,10 @@ constexpr bool has(Type processor_type, Register r) {
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}
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}
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constexpr bool has_extended_bus_output(Type processor_type) {
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return processor_type == Type::TWDC65816;
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}
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}
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#endif /* _502Selector_h */
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