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https://github.com/TomHarte/CLK.git
synced 2025-01-11 08:30:55 +00:00
Adds various bits of debugging detritus.
This commit is contained in:
Thomas Harte
parent
631a8a7421
commit
267e28e012
@ -107,7 +107,7 @@ class ConcreteMachine:
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adb_glu_->set_microcontroller_rom(*roms[2]);
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// Run only the currently-interesting self test.
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rom_[0x36402] = 2;
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// rom_[0x36402] = 2;
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// rom_[0x36403] = 0x7c; // ROM_CHECKSUM [working, when hacks like this are removed]
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// rom_[0x36404] = 0x6c;
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@ -129,8 +129,8 @@ class ConcreteMachine:
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// rom_[0x36403] = 0xdc; // CLOCK [broken]
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// rom_[0x36404] = 0x6c;
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rom_[0x36403] = 0x1b; // BAT_RAM [broken]
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rom_[0x36404] = 0x6e;
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// rom_[0x36403] = 0x1b; // BAT_RAM [broken]
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// rom_[0x36404] = 0x6e;
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// rom_[0x36403] = 0x11; // FDB (/ADB?) [broken]
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// rom_[0x36404] = 0x6f;
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@ -172,6 +172,7 @@ class ConcreteMachine:
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iwm_->set_drive(1, &drives35_[1]);
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// Randomise RAM contents.
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// std::srand(23);
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Memory::Fuzz(ram_);
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// Sync up initial values.
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@ -214,6 +215,7 @@ class ConcreteMachine:
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}
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Outputs::Speaker::Speaker *get_speaker() final {
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// return nullptr;
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return &speaker_;
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}
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@ -238,6 +240,93 @@ class ConcreteMachine:
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drives525_[1].set_activity_observer(observer, "Second 5.25\" Drive", true);
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}
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int handle_total_ = 0;
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bool dump_bank(const char *name, uint32_t address) {
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const auto handles = memory_.regions[memory_.region_map[0xe117]].read;
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printf("%s: ", name);
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int max = 52;
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uint32_t last_visited = 0;
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// Seed address.
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address = uint32_t(handles[address] | (handles[address+1] << 8) | (handles[address+2] << 16) | (handles[address+3] << 24));
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while(true) {
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if(!address) {
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printf("nil\n");
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break;
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}
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++handle_total_;
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if(address < 0xe11700 || address > 0xe11aff) {
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printf("Out of bounds error with address = %06x!\n", address);
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return false;
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}
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if((address - 0xe11700)%20) {
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printf("Address alignment error!\n");
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return false;
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}
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const uint32_t previous = uint32_t(handles[address+12] | (handles[address+13] << 8) | (handles[address+14] << 16) | (handles[address+15] << 24));
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const uint32_t next = uint32_t(handles[address+16] | (handles[address+17] << 8) | (handles[address+18] << 16) | (handles[address+19] << 24));
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const uint32_t pointer = uint32_t(handles[address] | (handles[address+1] << 8) | (handles[address+2] << 16) | (handles[address+3] << 24));
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const uint32_t size = uint32_t(handles[address+8] | (handles[address+9] << 8) | (handles[address+10] << 16) | (handles[address+11] << 24));
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printf("%06x (<- %06x | %06x ->) [%06x:%06x] -> \n", address, previous, next, pointer, size);
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if(previous && ((previous < 0xe0'0000) || (previous > 0xe2'0000))) {
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printf("Out of bounds error with previous = %06x! [%d && (%d || %d)]\n", previous, bool(previous), previous < 0xe0'0000, previous > 0xe2'0000);
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return false;
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}
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if((previous || last_visited) && (previous != last_visited)) {
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printf("Back link error!\n");
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return false;
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}
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last_visited = address;
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address = next;
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--max;
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if(!max) {
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printf("Endless loop error!\n");
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return false;
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}
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}
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return true;
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}
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bool has_seen_valid_memory_ = false;
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bool dump_memory_manager() {
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const auto pointers = memory_.regions[memory_.region_map[0xe116]].read;
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// Check for initial state having been reached.
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// if(!has_seen_valid_memory_) {
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// if(pointers[0xe11624]) return true;
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// for(int c = 0xe1160c; c < 0xe1161c; c++) {
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// if(pointers[c]) return true;
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// }
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// has_seen_valid_memory_ = true;
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// }
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// Output.
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printf("\nNumber of banks: %d\n", pointers[0xe11624]);
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bool result = true;
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handle_total_ = 0;
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result &= dump_bank("Mem", 0xe11600);
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result &= dump_bank("Purge", 0xe11604);
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result &= dump_bank("Free", 0xe11608);
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printf("Total: %d\n", handle_total_);
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if(handle_total_ != 51) return false;
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// result &= dump_bank("Bank 0", 0xe1160c);
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// result &= dump_bank("Bank 1", 0xe11610);
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// result &= dump_bank("Bank E0", 0xe11614);
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// result &= dump_bank("Bank E1", 0xe11618);
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// result &= dump_bank("Bank FF", 0xe1161c);
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return result;
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}
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// MARK: BusHandler.
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uint64_t total = 0;
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forceinline Cycles perform_bus_operation(const CPU::WDC65816::BusOperation operation, const uint32_t address, uint8_t *const value) {
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@ -569,9 +658,13 @@ class ConcreteMachine:
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is_1Mhz = true;
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break;
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// case Read(0xc037): case Write(0xc037):
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// // TODO: "Used during DMA as bank address"?
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// break;
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// C037 seems to be just a full-speed storage register.
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case Read(0xc037):
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*value = c037_;
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break;
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case Write(0xc037):
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c037_ = *value;
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break;
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case Read(0xc041):
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*value = megaii_interrupt_mask_;
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@ -735,7 +828,7 @@ class ConcreteMachine:
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// Temporary: log _potential_ mistakes.
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if((address_suffix < 0xc100 && address_suffix >= 0xc090) || (address_suffix < 0xc080)) {
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printf("Internal card-area access: %04x\n", address_suffix);
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log |= operation == CPU::WDC65816::BusOperation::ReadOpcode;
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// log |= operation == CPU::WDC65816::BusOperation::ReadOpcode;
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}
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if(is_read) {
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*value = rom_[rom_.size() - 65536 + address_suffix];
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@ -790,11 +883,12 @@ class ConcreteMachine:
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// get by adding periodic NOPs within their copy-to-shadow step.
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//
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// Maybe the interaction with 2.8Mhz refresh isn't as straightforward as I think?
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is_1Mhz |= region.flags & MemoryMap::Region::IsShadowed;
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const bool is_shadowed = IsShadowed(memory_, region, address);
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is_1Mhz |= is_shadowed;
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// Use a very broad test for flushing video: any write to $e0 or $e1, or any write that is shadowed.
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// TODO: at least restrict the e0/e1 test to possible video buffers!
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if((address >= 0xe0'0400 && address < 0xe1'a000) || region.flags & MemoryMap::Region::IsShadowed) {
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if((address >= 0xe0'0400 && address < 0xe1'a000) || is_shadowed) {
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video_.flush();
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}
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@ -805,25 +899,79 @@ class ConcreteMachine:
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if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
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assert(address);
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}
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// if(address >= 0xE11700 && address < 0xe11b00) {
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// printf("%06x %s %02x%s\n", address, isReadOperation(operation) ? "->" : "<-", *value,
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// operation == CPU::WDC65816::BusOperation::ReadOpcode ? " [*]" : "");
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// if(operation == CPU::WDC65816::BusOperation::Write && address >= 0xe11700 && address < 0xe11b00) {
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// dump_memory_manager();
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// printf("%04x <- %02x [%llu]\n", address, *value, static_cast<unsigned long long>(total));
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// }
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// if(address >= 0x00bc5d && address <= 0x00bc5f) {
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// printf("%06x %s %02x%s [%llu] [%p/%p]\n", address, isReadOperation(operation) ? "->" : "<-", *value,
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// operation == CPU::WDC65816::BusOperation::ReadOpcode ? " [*]" : "",
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// static_cast<unsigned long long>(total),
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// memory_.regions[memory_.region_map[0xe119]].read,
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// memory_.regions[memory_.region_map[0xe119]].write);
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// }
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// bool result = dump_bank(0, 0xe1160c);
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// result &= dump_bank(1, 0xe11610);
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// result &= dump_bank(0xe0, 0xe11614);
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// result &= dump_bank(0xe1, 0xe11618);
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// if(operation == CPU::WDC65816::BusOperation::Write && (
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// (address >= 0xe11700 && address <= 0xe11aff) ||
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// address == 0xe11624 || (address >= 0xe1160c && address < 0xe1161c))
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// ) {
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// // Test for breakages in the chain.
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// if(!dump_memory_manager()) {
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// printf("Broken at %llu\n", static_cast<unsigned long long>(total));
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// } else {
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// printf("Correct at %llu\n", static_cast<unsigned long long>(total));
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// }
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// }
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// if(operation == CPU::WDC65816::BusOperation::Write && (address >= 0xe11750 + 16 && address < 0xe11750 + 20)) {
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// printf("%06x <- %02x [%llu]\n", address, *value, static_cast<unsigned long long>(total));
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// }
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// if(memory_.regions[memory_.region_map[0x755b]].read[0x755b4d] == 0x7f) {
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// printf("%llu\n", static_cast<unsigned long long>(total));
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// }
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// if(operation == CPU::WDC65816::BusOperation::Write && address == 0x755b4d) {
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// printf("%04x <- %02x [%llu]\n", address, *value, static_cast<unsigned long long>(total));
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// }
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// log |= (total == 611808545);
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// log |= (total == 663201455);
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if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
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// log |= total == 502083045;
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// log |= total == 502070045;
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// log |= total == 497920695;
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// log |= total == 495795545;
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// log |= total == 342435845;
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// log |= total == 492330040;
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// if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
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// log |= address == 0xfc0fa6;
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// log &= address != 0xfc0fa8;
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// log |= address == 0xfc01ba;
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// log |= address == 0xfc10fd;
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// log &= address != 0xff4a73;
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// log = (address >= 0xff6cdc) && (address < 0xff6d43);
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// log = (address >= 0x00d300) && (address < 0x00d600);
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}
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// if(address == 0xfc02b1) {
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// dump_memory_manager();
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// }
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// }
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// log &= !((operation == CPU::WDC65816::BusOperation::ReadOpcode) && ((address < 0xff6a2c) || (address >= 0xff6a9c)));
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// if(address == 0x00bca9 && operation == CPU::WDC65816::BusOperation::Write && !*value) {
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// printf("%06x <- %02x [%d]\n", address, *value, static_cast<unsigned long long>(total));
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// }
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// log |= (address == 0x755b4d);
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if(log) {
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printf("%06x %s %02x [%s]", address, isReadOperation(operation) ? "->" : "<-", *value, (is_1Mhz || (speed_register_ & motor_flags_)) ? "1.0" : "2.8");
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if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
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@ -965,8 +1113,9 @@ class ConcreteMachine:
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// MARK: - Memory storage.
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std::vector<uint8_t> ram_{};
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std::vector<uint8_t> ram_;
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std::vector<uint8_t> rom_;
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uint8_t c037_ = 0;
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// MARK: - Other components.
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