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Implement RTE, RTS, RTR.

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This commit is contained in:
Thomas Harte 2022-05-22 21:16:38 -04:00
parent 4e21cdfc63
commit 269263eecf
2 changed files with 60 additions and 2 deletions
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4
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
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@ -184,8 +184,8 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
@"nbcd_pea.json", @"nbcd_pea.json",
@"neg_not.json", @"neg_not.json",
@"negx_clr.json", @"negx_clr.json",
// @"rtr.json", @"rtr.json",
// @"rts.json", @"rts.json",
@"swap.json", @"swap.json",
@"tas.json", @"tas.json",
@"tst.json", @"tst.json",

58
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
View File

@ -167,6 +167,9 @@ enum ExecutionState: int {
PEA, PEA,
TAS, TAS,
MOVEtoCCRSR, MOVEtoCCRSR,
RTR,
RTE,
RTS,
}; };
// MARK: - The state machine. // MARK: - The state machine.
@ -742,6 +745,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToStateSpecific(CalcEffectiveAddress); MoveToStateSpecific(CalcEffectiveAddress);
}); });
StdCASE(RTR, MoveToStateSpecific(RTR));
StdCASE(RTE, MoveToStateSpecific(RTE));
StdCASE(RTS, MoveToStateSpecific(RTS));
default: default:
assert(false); assert(false);
} }
@ -1988,6 +1995,57 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Prefetch(); Prefetch();
MoveToStateSpecific(Decode); MoveToStateSpecific(Decode);
//
// RTR, RTS, RTE
//
BeginState(RTS):
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
SetDataAddress(registers_[15].l);
Access(program_counter_.high);
registers_[15].l += 2;
Access(program_counter_.low);
registers_[15].l += 2;
Prefetch();
Prefetch();
MoveToStateSpecific(Decode);
BeginState(RTE):
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
SetDataAddress(registers_[15].l);
Access(program_counter_.high);
registers_[15].l += 2;
Access(program_counter_.low);
registers_[15].l += 2;
Access(temporary_value_.low);
registers_[15].l += 2;
status_.set_status(temporary_value_.w);
Prefetch();
Prefetch();
MoveToStateSpecific(Decode);
BeginState(RTR):
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
SetDataAddress(registers_[15].l);
registers_[15].l += 2;
Access(program_counter_.high);
registers_[15].l += 2;
Access(program_counter_.low);
registers_[15].l -= 4;
Access(temporary_value_.low);
registers_[15].l += 6;
status_.set_ccr(temporary_value_.w);
Prefetch();
Prefetch();
MoveToStateSpecific(Decode);
// //
// Various states TODO. // Various states TODO.
// //