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Corrects EA usage for ADDA and SUBA.

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This commit is contained in:
Thomas Harte 2019-04-19 23:02:41 -04:00
parent a49f516265
commit 2cac4b0d74
3 changed files with 10 additions and 8 deletions
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8
OSBindings/Mac/Clock SignalTests/QLTests.mm
View File

@ -71,20 +71,20 @@ class QL: public CPU::MC68000::BusHandler {
case Microcycle::SelectWord | Microcycle::Read: case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = is_peripheral ? peripheral_result : base[word_address]; cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
// if(!(cycle.operation & Microcycle::IsProgram)) printf("[word r %08x -> %04x] ", *cycle.address, cycle.value->full); if(!(cycle.operation & Microcycle::IsProgram)) printf("[word r %08x -> %04x]\n ", *cycle.address, cycle.value->full);
break; break;
case Microcycle::SelectByte | Microcycle::Read: case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift(); cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
// if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte r %08x -> %02x] ", *cycle.address, cycle.value->halves.low); if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte r %08x -> %02x]\n", *cycle.address, cycle.value->halves.low);
break; break;
case Microcycle::SelectWord: case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral)); assert(!(is_rom && !is_peripheral));
// if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x] ", cycle.value->full, *cycle.address); if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x]\n", cycle.value->full, *cycle.address);
if(!is_peripheral) base[word_address] = cycle.value->full; if(!is_peripheral) base[word_address] = cycle.value->full;
break; break;
case Microcycle::SelectByte: case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral)); assert(!(is_rom && !is_peripheral));
// if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x] ", cycle.value->halves.low, *cycle.address); if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x]\n", cycle.value->halves.low, *cycle.address);
if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask())); if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break; break;
} }

2
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -63,6 +63,8 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
should_log |= program_counter_.full > 0x286; should_log |= program_counter_.full > 0x286;
if(should_log) { if(should_log) {
std::cout << "a5:" << std::setw(8) << std::setfill('0') << address_[5].full << " ";
std::cout << "a6:" << std::setw(8) << std::setfill('0') << address_[6].full << " ";
std::cout << "a7:" << std::setw(8) << std::setfill('0') << address_[7].full << " "; std::cout << "a7:" << std::setw(8) << std::setfill('0') << address_[7].full << " ";
if(is_supervisor_) { if(is_supervisor_) {
std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " "; std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " ";

8
Processors/68000/Implementation/68000Storage.cpp
View File

@ -1272,14 +1272,14 @@ struct ProcessorStorageConstructor {
case bw(d16An): // ADDA/SUBA.w (d16, An), An case bw(d16An): // ADDA/SUBA.w (d16, An), An
case bw(d8AnXn): // ADDA/SUBA.w (d8, An, Xn), An case bw(d8AnXn): // ADDA/SUBA.w (d8, An, Xn), An
op( calc_action_for_mode(mode) | MicroOp::SourceMask, op( calc_action_for_mode(mode) | MicroOp::SourceMask,
seq(pseq("np nr np nn", mode), { ea(1) })); seq(pseq("np nr np nn", mode), { ea(0) }));
op(Action::PerformOperation); op(Action::PerformOperation);
break; break;
case l(d16An): // ADDA/SUBA.l (d16, An), An case l(d16An): // ADDA/SUBA.l (d16, An), An
case l(d8AnXn): // ADDA/SUBA.l (d8, An, Xn), An case l(d8AnXn): // ADDA/SUBA.l (d8, An, Xn), An
op( calc_action_for_mode(mode) | MicroOp::SourceMask, op( calc_action_for_mode(mode) | MicroOp::SourceMask,
seq(pseq("np nR+ nr np n", mode), { ea(1), ea(1) })); seq(pseq("np nR+ nr np n", mode), { ea(0), ea(0) }));
op(Action::PerformOperation); op(Action::PerformOperation);
break; break;
@ -1287,7 +1287,7 @@ struct ProcessorStorageConstructor {
op(Action::None, seq("np")); op(Action::None, seq("np"));
case bw(XXXw): // ADDA/SUBA.w (xxx).w, An case bw(XXXw): // ADDA/SUBA.w (xxx).w, An
op( address_assemble_for_mode(mode) | MicroOp::SourceMask, op( address_assemble_for_mode(mode) | MicroOp::SourceMask,
seq("np nr np nn", { ea(1) })); seq("np nr np nn", { ea(0) }));
op(Action::PerformOperation); op(Action::PerformOperation);
break; break;
@ -1295,7 +1295,7 @@ struct ProcessorStorageConstructor {
op(Action::None, seq("np")); op(Action::None, seq("np"));
case l(XXXw): // ADDA/SUBA.l (xxx).w, An case l(XXXw): // ADDA/SUBA.l (xxx).w, An
op( address_assemble_for_mode(mode) | MicroOp::SourceMask, op( address_assemble_for_mode(mode) | MicroOp::SourceMask,
seq("np nR+ nr np n", { ea(1), ea(1) })); seq("np nR+ nr np n", { ea(0), ea(0) }));
op( Action::PerformOperation); op( Action::PerformOperation);
break; break;