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Exit gracefully upon a STP or WAI.
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a23b0f5122
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@ -38,6 +38,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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--opcodes_remaining;
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if(!opcodes_remaining) {
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cycles.pop_back();
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pc_overshoot = -1;
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throw StopException();
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}
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case BusOperation::Read:
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@ -55,7 +56,12 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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cycle.value = ram[address] = *value;
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break;
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default: break;
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case BusOperation::Ready:
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case BusOperation::None:
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throw StopException();
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break;
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default: assert(false);
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}
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// Don't occupy any bonus time.
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@ -66,6 +72,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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ram.clear();
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inventions.clear();
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cycles.clear();
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pc_overshoot = 0;
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using Register = CPU::MOS6502Esque::Register;
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const uint32_t pc =
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@ -75,6 +82,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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}
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int opcodes_remaining = 0;
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int pc_overshoot = 0;
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struct Cycle {
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CPU::MOS6502Esque::BusOperation operation;
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@ -89,7 +97,6 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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BusHandler() : processor(*this) {
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// Never run the official reset procedure.
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processor.set_power_on(false);
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}
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};
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@ -188,7 +195,7 @@ void print_ram(FILE *file, const std::unordered_map<uint32_t, uint8_t> &data) {
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// Dump final state.
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fprintf(target, "}, \"final\": {");
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print_registers(target, handler.processor, -1);
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print_registers(target, handler.processor, handler.pc_overshoot);
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print_ram(target, handler.ram);
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fprintf(target, "}, ");
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