mirror of
https://github.com/TomHarte/CLK.git
synced 2024-06-09 17:29:36 +00:00
As it continues to swell, factor out the junk.
This commit is contained in:
Thomas Harte
parent
335d13d06d
commit
31979649c6
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@ -41,6 +41,282 @@ Log::Logger<Log::Source::Archimedes> logger;
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namespace Archimedes {
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#ifndef NDEBUG
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template <InstructionSet::ARM::Model model, typename Executor>
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struct HackyDebugger {
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void notify(uint32_t address, uint32_t instruction, Executor &executor) {
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pc_history[pc_history_ptr] = address;
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pc_history_ptr = (pc_history_ptr + 1) % pc_history.size();
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// if(
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// executor_.pc() > 0x038021d0 &&
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// last_r1 != executor_.registers()[1]
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// ||
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// (
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// last_link != executor_.registers()[14] ||
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// last_r0 != executor_.registers()[0] ||
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// last_r10 != executor_.registers()[10] ||
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// last_r1 != executor_.registers()[1]
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// )
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// ) {
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// logger.info().append("%08x modified R14 to %08x; R0 to %08x; R10 to %08x; R1 to %08x",
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// last_pc,
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// executor_.registers()[14],
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// executor_.registers()[0],
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// executor_.registers()[10],
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// executor_.registers()[1]
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// );
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// logger.info().append("%08x modified R1 to %08x",
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// last_pc,
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// executor_.registers()[1]
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// );
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// last_link = executor_.registers()[14];
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// last_r0 = executor_.registers()[0];
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// last_r10 = executor_.registers()[10];
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// last_r1 = executor_.registers()[1];
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// }
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// if(executor_.pc() == 0x03801ed8 || (executor_.registers()[9] == 0x00ff'0000 && executor_.registers()[9] != last_r9)) {
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// printf("At %08x; after last PC %08x and %zu ago was %08x; r9 is %08x [%d]\n",
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// executor_.pc(),
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// pc_history[(pc_history_ptr - 2 + pc_history.size()) % pc_history.size()],
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// pc_history.size(),
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// pc_history[pc_history_ptr],
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// executor_.registers()[9],
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// executor_.registers()[9] != last_r9);
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// }
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// last_r9 = executor_.registers()[9];
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// log |= executor_.pc() == 0x03801ebc;
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// log |= instr_count == 72766815;
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// log &= executor_.pc() != 0x000000a0;
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// log = (executor_.pc() == 0x038162afc) || (executor_.pc() == 0x03824b00);
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// log |= instruction & ;
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// The following has the effect of logging all taken SWIs and their return codes.
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if(
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(instruction & 0x0f00'0000) == 0x0f00'0000 &&
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executor.registers().test(InstructionSet::ARM::Condition(instruction >> 28))
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) {
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if(instruction & 0x2'0000) {
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swis.emplace_back();
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swis.back().opcode = instruction;
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swis.back().address = executor.pc();
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swis.back().return_address = executor.registers().pc(4);
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for(int c = 0; c < 10; c++) swis.back().regs[c] = executor.registers()[uint32_t(c)];
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// Possibly capture more detail.
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//
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// Cf. http://productsdb.riscos.com/support/developers/prm_index/numswilist.html
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uint32_t pointer = 0;
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switch(instruction & 0xfd'ffff) {
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case 0x41501:
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swis.back().swi_name = "MessageTrans_OpenFile";
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// R0: pointer to file descriptor; R1: pointer to filename; R2: pointer to hold file data.
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// (R0 and R1 are in the RMA if R2 = 0)
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pointer = executor.registers()[1];
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break;
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case 0x41502:
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swis.back().swi_name = "MessageTrans_Lookup";
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break;
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case 0x41506:
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swis.back().swi_name = "MessageTrans_ErrorLookup";
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break;
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case 0x4028a:
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swis.back().swi_name = "Podule_EnumerateChunksWithInfo";
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break;
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case 0x4000a:
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swis.back().swi_name = "Econet_ReadLocalStationAndNet";
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break;
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case 0x4000e:
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swis.back().swi_name = "Econet_SetProtection";
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break;
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case 0x40015:
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swis.back().swi_name = "Econet_ClaimPort";
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break;
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case 0x40541:
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swis.back().swi_name = "FileCore_Create";
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break;
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case 0x80156:
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case 0x8015b:
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swis.back().swi_name = "PDriver_MiscOpForDriver";
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break;
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case 0x05:
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swis.back().swi_name = "OS_CLI";
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pointer = executor.registers()[0];
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break;
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case 0x0d:
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swis.back().swi_name = "OS_Find";
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if(executor.registers()[0] >= 0x40) {
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pointer = executor.registers()[1];
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}
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break;
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case 0x1d:
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swis.back().swi_name = "OS_Heap";
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break;
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case 0x1e:
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swis.back().swi_name = "OS_Module";
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break;
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case 0x20:
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swis.back().swi_name = "OS_Release";
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break;
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case 0x21:
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swis.back().swi_name = "OS_ReadUnsigned";
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break;
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case 0x23:
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swis.back().swi_name = "OS_ReadVarVal";
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// R0: pointer to variable name.
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pointer = executor.registers()[0];
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break;
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case 0x24:
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swis.back().swi_name = "OS_SetVarVal";
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// R0: pointer to variable name.
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pointer = executor.registers()[0];
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break;
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case 0x26:
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swis.back().swi_name = "OS_GSRead";
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break;
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case 0x27:
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swis.back().swi_name = "OS_GSTrans";
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pointer = executor.registers()[0];
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break;
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case 0x29:
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swis.back().swi_name = "OS_FSControl";
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break;
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case 0x2a:
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swis.back().swi_name = "OS_ChangeDynamicArea";
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break;
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case 0x4c:
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swis.back().swi_name = "OS_ReleaseDeviceVector";
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break;
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case 0x43057:
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swis.back().swi_name = "Territory_LowerCaseTable";
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break;
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case 0x43058:
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swis.back().swi_name = "Territory_UpperCaseTable";
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break;
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case 0x42fc0:
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swis.back().swi_name = "Portable_Speed";
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break;
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case 0x42fc1:
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swis.back().swi_name = "Portable_Control";
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break;
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}
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if(pointer) {
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while(true) {
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uint8_t next;
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executor.bus.template read<uint8_t>(pointer, next, InstructionSet::ARM::Mode::Supervisor, false);
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++pointer;
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if(next < 32) break;
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swis.back().value_name.push_back(static_cast<char>(next));
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}
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}
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}
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if(executor.registers().pc_status(0) & InstructionSet::ARM::ConditionCode::Overflow) {
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logger.error().append("SWI called with V set");
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}
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}
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if(!swis.empty() && executor.pc() == swis.back().return_address) {
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// Overflow set => SWI failure.
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auto &back = swis.back();
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if(executor.registers().pc_status(0) & InstructionSet::ARM::ConditionCode::Overflow) {
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auto info = logger.info();
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info.append("failed swi ");
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if(back.swi_name.empty()) {
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info.append("&%x", back.opcode & 0xfd'ffff);
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} else {
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info.append("%s", back.swi_name.c_str());
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}
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if(!back.value_name.empty()) {
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info.append(" %s", back.value_name.c_str());
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}
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info.append(" @ %08x ", back.address);
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for(uint32_t c = 0; c < 10; c++) {
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info.append("r%d:%08x ", c, back.regs[c]);
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}
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}
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swis.pop_back();
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}
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if(log) {
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InstructionSet::ARM::Disassembler<model> disassembler;
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InstructionSet::ARM::dispatch<model>(instruction, disassembler);
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auto info = logger.info();
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info.append("[%d] %08x: %08x\t\t%s\t prior:[",
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instr_count,
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executor.pc(),
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instruction,
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disassembler.last().to_string(executor.pc()).c_str());
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for(uint32_t c = 0; c < 15; c++) {
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info.append("r%d:%08x ", c, executor.registers()[c]);
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}
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info.append("]");
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}
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opcodes.insert(instruction);
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if(accumulate) {
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int c = 0;
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for(auto instr : opcodes) {
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printf("0x%08x, ", instr);
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++c;
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if(!(c&15)) printf("\n");
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}
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accumulate = false;
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}
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++instr_count;
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}
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private:
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std::array<uint32_t, 75> pc_history;
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std::size_t pc_history_ptr = 0;
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uint32_t instr_count = 0;
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struct SWICall {
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uint32_t opcode;
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uint32_t address;
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uint32_t regs[10];
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uint32_t return_address;
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std::string value_name;
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std::string swi_name;
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};
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std::vector<SWICall> swis;
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uint32_t last_pc = 0;
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// uint32_t last_r9 = 0;
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bool log = false;
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bool accumulate = true;
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std::set<uint32_t> opcodes;
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};
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#else
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template <typename Executor>
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struct HackyDebugger {
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void notify(uint32_t, uint32_t, Executor &) {}
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};
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#endif
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class ConcreteMachine:
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public Machine,
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public MachineTypes::MappedKeyboardMachine,
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@ -127,12 +403,6 @@ class ConcreteMachine:
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return;
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}
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if(requests & InterruptRequests::IRQ) {
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// logger.info().append("[%d] IRQ at %08x prior:[r13:%08x r14:%08x]",
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// instr_count,
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// executor_.pc(),
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// executor_.registers()[13],
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// executor_.registers()[14]);
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executor_.registers().interrupt<Exception::IRQ>();
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}
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}
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@ -150,10 +420,6 @@ class ConcreteMachine:
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return executor_.bus.video().crt().get_scaled_scan_status();
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}
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std::array<uint32_t, 75> pc_history;
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std::size_t pc_history_ptr = 0;
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uint32_t instr_count = 0;
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// MARK: - TimedMachine.
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void run_for(Cycles cycles) override {
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macro_counter_ += cycles.as<int>();
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@ -170,275 +436,19 @@ class ConcreteMachine:
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}
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int video_divider_ = 1;
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std::set<uint32_t> opcodes;
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void tick_cpu() {
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struct SWICall {
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uint32_t opcode;
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uint32_t address;
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uint32_t regs[10];
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uint32_t return_address;
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std::string value_name;
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std::string swi_name;
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};
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static std::vector<SWICall> swis;
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static uint32_t last_pc = 0;
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// static uint32_t last_r9 = 0;
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static bool log = false;
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static bool accumulate = true;
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// if(executor_.pc() == 0x03801ed8 || (executor_.registers()[9] == 0x00ff'0000 && executor_.registers()[9] != last_r9)) {
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// printf("At %08x; after last PC %08x and %zu ago was %08x; r9 is %08x [%d]\n",
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// executor_.pc(),
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// pc_history[(pc_history_ptr - 2 + pc_history.size()) % pc_history.size()],
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// pc_history.size(),
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// pc_history[pc_history_ptr],
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// executor_.registers()[9],
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// executor_.registers()[9] != last_r9);
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// }
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// last_r9 = executor_.registers()[9];
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uint32_t instruction;
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pc_history[pc_history_ptr] = executor_.pc();
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pc_history_ptr = (pc_history_ptr + 1) % pc_history.size();
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if(!executor_.bus.read(executor_.pc(), instruction, executor_.registers().mode(), false)) {
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logger.info().append("Prefetch abort at %08x; last good was at %08x", executor_.pc(), last_pc);
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// logger.info().append("Prefetch abort at %08x; last good was at %08x", executor_.pc(), last_pc);
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executor_.prefetch_abort();
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// TODO: does a double abort cause a reset?
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executor_.bus.read(executor_.pc(), instruction, executor_.registers().mode(), false);
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} else {
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last_pc = executor_.pc();
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}
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// TODO: pipeline prefetch?
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// log |= executor_.pc() == 0x03801ebc;
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// log |= instr_count == 72766815;
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// log &= executor_.pc() != 0x000000a0;
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// log = (executor_.pc() == 0x038162afc) || (executor_.pc() == 0x03824b00);
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// log |= instruction & ;
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// The following has the effect of logging all taken SWIs and their return codes.
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if(
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(instruction & 0x0f00'0000) == 0x0f00'0000 &&
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executor_.registers().test(InstructionSet::ARM::Condition(instruction >> 28))
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) {
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if(instruction & 0x2'0000) {
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swis.emplace_back();
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swis.back().opcode = instruction;
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swis.back().address = executor_.pc();
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swis.back().return_address = executor_.registers().pc(4);
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for(int c = 0; c < 10; c++) swis.back().regs[c] = executor_.registers()[uint32_t(c)];
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// Possibly capture more detail.
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//
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// Cf. http://productsdb.riscos.com/support/developers/prm_index/numswilist.html
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uint32_t pointer = 0;
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switch(instruction & 0xfd'ffff) {
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case 0x41501:
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swis.back().swi_name = "MessageTrans_OpenFile";
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// R0: pointer to file descriptor; R1: pointer to filename; R2: pointer to hold file data.
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// (R0 and R1 are in the RMA if R2 = 0)
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pointer = executor_.registers()[1];
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break;
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case 0x41502:
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swis.back().swi_name = "MessageTrans_Lookup";
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break;
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case 0x41506:
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swis.back().swi_name = "MessageTrans_ErrorLookup";
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break;
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case 0x4028a:
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swis.back().swi_name = "Podule_EnumerateChunksWithInfo";
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break;
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case 0x4000a:
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swis.back().swi_name = "Econet_ReadLocalStationAndNet";
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break;
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case 0x4000e:
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swis.back().swi_name = "Econet_SetProtection";
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break;
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case 0x40015:
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swis.back().swi_name = "Econet_ClaimPort";
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break;
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case 0x40541:
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swis.back().swi_name = "FileCore_Create";
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break;
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case 0x80156:
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case 0x8015b:
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swis.back().swi_name = "PDriver_MiscOpForDriver";
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break;
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case 0x05:
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swis.back().swi_name = "OS_CLI";
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pointer = executor_.registers()[0];
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break;
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case 0x0d:
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swis.back().swi_name = "OS_Find";
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if(executor_.registers()[0] >= 0x40) {
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pointer = executor_.registers()[1];
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}
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break;
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case 0x1d:
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swis.back().swi_name = "OS_Heap";
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break;
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case 0x1e:
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swis.back().swi_name = "OS_Module";
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break;
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case 0x20:
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swis.back().swi_name = "OS_Release";
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break;
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case 0x21:
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swis.back().swi_name = "OS_ReadUnsigned";
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break;
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case 0x23:
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swis.back().swi_name = "OS_ReadVarVal";
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// R0: pointer to variable name.
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pointer = executor_.registers()[0];
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break;
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case 0x24:
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swis.back().swi_name = "OS_SetVarVal";
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// R0: pointer to variable name.
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pointer = executor_.registers()[0];
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break;
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case 0x26:
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swis.back().swi_name = "OS_GSRead";
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break;
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case 0x27:
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swis.back().swi_name = "OS_GSTrans";
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pointer = executor_.registers()[0];
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break;
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case 0x29:
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swis.back().swi_name = "OS_FSControl";
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break;
|
||||
case 0x2a:
|
||||
swis.back().swi_name = "OS_ChangeDynamicArea";
|
||||
break;
|
||||
|
||||
case 0x4c:
|
||||
swis.back().swi_name = "OS_ReleaseDeviceVector";
|
||||
break;
|
||||
|
||||
case 0x43057:
|
||||
swis.back().swi_name = "Territory_LowerCaseTable";
|
||||
break;
|
||||
case 0x43058:
|
||||
swis.back().swi_name = "Territory_UpperCaseTable";
|
||||
break;
|
||||
|
||||
case 0x42fc0:
|
||||
swis.back().swi_name = "Portable_Speed";
|
||||
break;
|
||||
case 0x42fc1:
|
||||
swis.back().swi_name = "Portable_Control";
|
||||
break;
|
||||
}
|
||||
|
||||
if(pointer) {
|
||||
while(true) {
|
||||
uint8_t next;
|
||||
executor_.bus.template read<uint8_t>(pointer, next, InstructionSet::ARM::Mode::Supervisor, false);
|
||||
++pointer;
|
||||
|
||||
if(next < 32) break;
|
||||
swis.back().value_name.push_back(static_cast<char>(next));
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(executor_.registers().pc_status(0) & InstructionSet::ARM::ConditionCode::Overflow) {
|
||||
logger.error().append("SWI called with V set");
|
||||
}
|
||||
}
|
||||
if(!swis.empty() && executor_.pc() == swis.back().return_address) {
|
||||
// Overflow set => SWI failure.
|
||||
auto &back = swis.back();
|
||||
if(executor_.registers().pc_status(0) & InstructionSet::ARM::ConditionCode::Overflow) {
|
||||
auto info = logger.info();
|
||||
|
||||
info.append("failed swi ");
|
||||
if(back.swi_name.empty()) {
|
||||
info.append("&%x", back.opcode & 0xfd'ffff);
|
||||
} else {
|
||||
info.append("%s", back.swi_name.c_str());
|
||||
}
|
||||
|
||||
if(!back.value_name.empty()) {
|
||||
info.append(" %s", back.value_name.c_str());
|
||||
}
|
||||
|
||||
info.append(" @ %08x ", back.address);
|
||||
for(uint32_t c = 0; c < 10; c++) {
|
||||
info.append("r%d:%08x ", c, back.regs[c]);
|
||||
}
|
||||
}
|
||||
|
||||
swis.pop_back();
|
||||
}
|
||||
|
||||
if(log) {
|
||||
InstructionSet::ARM::Disassembler<arm_model> disassembler;
|
||||
InstructionSet::ARM::dispatch<arm_model>(instruction, disassembler);
|
||||
|
||||
auto info = logger.info();
|
||||
info.append("[%d] %08x: %08x\t\t%s\t prior:[",
|
||||
instr_count,
|
||||
executor_.pc(),
|
||||
instruction,
|
||||
disassembler.last().to_string(executor_.pc()).c_str());
|
||||
for(uint32_t c = 0; c < 15; c++) {
|
||||
info.append("r%d:%08x ", c, executor_.registers()[c]);
|
||||
}
|
||||
info.append("]");
|
||||
}
|
||||
opcodes.insert(instruction);
|
||||
if(accumulate) {
|
||||
int c = 0;
|
||||
for(auto instr : opcodes) {
|
||||
printf("0x%08x, ", instr);
|
||||
++c;
|
||||
if(!(c&15)) printf("\n");
|
||||
}
|
||||
accumulate = false;
|
||||
}
|
||||
// logger.info().append("%08x: %08x", executor_.pc(), instruction);
|
||||
debugger_.notify(executor_.pc(), instruction, executor_);
|
||||
InstructionSet::ARM::execute(instruction, executor_);
|
||||
++instr_count;
|
||||
|
||||
// if(
|
||||
// executor_.pc() > 0x038021d0 &&
|
||||
// last_r1 != executor_.registers()[1]
|
||||
// ||
|
||||
// (
|
||||
// last_link != executor_.registers()[14] ||
|
||||
// last_r0 != executor_.registers()[0] ||
|
||||
// last_r10 != executor_.registers()[10] ||
|
||||
// last_r1 != executor_.registers()[1]
|
||||
// )
|
||||
// ) {
|
||||
// logger.info().append("%08x modified R14 to %08x; R0 to %08x; R10 to %08x; R1 to %08x",
|
||||
// last_pc,
|
||||
// executor_.registers()[14],
|
||||
// executor_.registers()[0],
|
||||
// executor_.registers()[10],
|
||||
// executor_.registers()[1]
|
||||
// );
|
||||
// logger.info().append("%08x modified R1 to %08x",
|
||||
// last_pc,
|
||||
// executor_.registers()[1]
|
||||
// );
|
||||
// last_link = executor_.registers()[14];
|
||||
// last_r0 = executor_.registers()[0];
|
||||
// last_r10 = executor_.registers()[10];
|
||||
// last_r1 = executor_.registers()[1];
|
||||
// }
|
||||
}
|
||||
|
||||
void tick_timers() { executor_.bus.tick_timers(); }
|
||||
|
|
@ -476,7 +486,11 @@ class ConcreteMachine:
|
|||
|
||||
// MARK: - ARM execution
|
||||
static constexpr auto arm_model = InstructionSet::ARM::Model::ARMv2;
|
||||
InstructionSet::ARM::Executor<arm_model, MemoryController<ConcreteMachine, ConcreteMachine>> executor_;
|
||||
using Executor = InstructionSet::ARM::Executor<arm_model, MemoryController<ConcreteMachine, ConcreteMachine>>;
|
||||
Executor executor_;
|
||||
|
||||
// MARK: - Yucky, temporary junk.
|
||||
HackyDebugger<arm_model, Executor> debugger_;
|
||||
};
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user