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Implements MOVEM to M with an implicit type conversion.
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Thomas Harte
parent
1003e70b5e
commit
325af677d3
@ -354,34 +354,75 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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MOVEM: multi-word moves.
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*/
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#define setup_movem(words_per_reg) \
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/* Count the number of long words to move. */ \
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size_t total_to_move = 0; \
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auto mask = next_word_; \
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while(mask) { \
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total_to_move += mask&1; \
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mask >>= 1; \
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} \
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\
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/* Twice that many words plus one will need to be moved */ \
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bus_program = movem_reads_steps_ + (64 - total_to_move*words_per_reg)*2; \
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\
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/* Fill in the proper addresses and targets. */ \
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const auto mode = (decoded_instruction_ >> 3) & 7; \
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uint32_t start_address; \
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if(mode <= 4) { \
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start_address = active_program_->source_address->full; \
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} else { \
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start_address = effective_address_[1].full; \
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} \
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\
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auto step = bus_program; \
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uint32_t *address_storage = movem_addresses_; \
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mask = next_word_; \
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#define setup_movem(words_per_reg, base) \
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/* Count the number of long words to move. */ \
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size_t total_to_move = 0; \
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auto mask = next_word_; \
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while(mask) { \
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total_to_move += mask&1; \
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mask >>= 1; \
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} \
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\
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/* Twice that many words plus one will need to be moved */ \
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bus_program = base + (64 - total_to_move*words_per_reg)*2; \
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\
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/* Fill in the proper addresses and targets. */ \
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const auto mode = (decoded_instruction_ >> 3) & 7; \
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uint32_t start_address; \
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if(mode <= 4) { \
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start_address = active_program_->destination_address->full; \
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} else { \
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start_address = effective_address_[1].full; \
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} \
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\
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auto step = bus_program; \
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uint32_t *address_storage = movem_addresses_; \
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mask = next_word_; \
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int offset = 0;
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#define write_address_sequence_long(address_step, offset_step, l, h) \
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while(mask) { \
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if(mask&1) { \
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address_storage[0] = start_address; \
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address_storage[1] = start_address + address_step; \
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\
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step[0].microcycle.address = step[1].microcycle.address = address_storage; \
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step[2].microcycle.address = step[3].microcycle.address = address_storage + 1; \
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\
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const auto target = (offset > 7) ? &address_[offset&7] : &data_[offset]; \
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step[h].microcycle.value = step[h+1].microcycle.value = &target->halves.high; \
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step[l].microcycle.value = step[l+1].microcycle.value = &target->halves.low; \
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\
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start_address += address_step*2; \
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address_storage += 2; \
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step += 4; \
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} \
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mask >>= 1; \
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offset += offset_step; \
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}
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#define write_address_sequence_word(address_step, offset_step) \
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while(mask) { \
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if(mask&1) { \
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address_storage[0] = start_address; \
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\
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step[0].microcycle.address = step[1].microcycle.address = address_storage; \
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\
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const auto target = (offset > 7) ? &address_[offset&7] : &data_[offset]; \
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step[0].microcycle.value = step[1].microcycle.value = &target->halves.low; \
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\
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start_address += address_step; \
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++ address_storage; \
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step += 2; \
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} \
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mask >>= 1; \
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offset += offset_step; \
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}
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case Operation::MOVEMtoRl: {
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setup_movem(2);
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setup_movem(2, movem_reads_steps_);
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// Everything for move to registers is based on an incrementing
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// address; per M68000PRM:
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@ -389,26 +430,11 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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// "[If using the postincrement addressing mode then] the incremented address
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// register contains the address of the last operand loaded plus the operand length.
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// If the addressing register is also loaded from memory, the memory value is ignored
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// and the register is written with the postincre- mented effective address."
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while(mask) {
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if(mask&1) {
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address_storage[0] = start_address;
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address_storage[1] = start_address + 2;
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step[0].microcycle.address = step[1].microcycle.address = address_storage;
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step[2].microcycle.address = step[3].microcycle.address = address_storage + 1;
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const auto target = (offset > 7) ? &address_[offset&7] : &data_[offset];
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step[0].microcycle.value = step[1].microcycle.value = &target->halves.high;
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step[2].microcycle.value = step[3].microcycle.value = &target->halves.low;
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start_address += 4;
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address_storage += 2;
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step += 4;
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}
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mask >>= 1;
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++offset;
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}
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// and the register is written with the postincremented effective address."
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//
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// The latter part is dealt with by MicroOp::Action::MOVEMtoRComplete, which also
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// does any necessary sign extension.
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write_address_sequence_long(2, 1, 0, 2);
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// MOVEM to R always reads one word too many.
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address_storage[0] = start_address;
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@ -418,24 +444,8 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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} break;
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case Operation::MOVEMtoRw: {
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setup_movem(1);
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while(mask) {
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if(mask&1) {
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address_storage[0] = start_address;
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step[0].microcycle.address = step[1].microcycle.address = address_storage;
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const auto target = (offset > 7) ? &address_[offset&7] : &data_[offset];
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step[0].microcycle.value = step[1].microcycle.value = &target->halves.low;
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start_address += 2;
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++ address_storage;
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step += 2;
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}
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mask >>= 1;
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++offset;
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}
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setup_movem(1, movem_reads_steps_);
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write_address_sequence_word(2, 1);
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// MOVEM to R always reads one word too many.
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address_storage[0] = start_address;
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@ -445,14 +455,43 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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} break;
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case Operation::MOVEMtoMl: {
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setup_movem(2);
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setup_movem(2, movem_writes_steps_);
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// MOVEM to M counts downwards and enumerates the registers in reverse order
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// if subject to the predecrementing mode; otherwise it counts upwards and
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// operates exactly as does MOVEM to R.
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//
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// Note also: "The MC68000 and MC68010 write the initial register value
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// (not decremented) [when writing a register that is providing
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// pre-decrementing addressing]."
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//
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// Hence the decrementing register (if any) is updated
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// by MicroOp::Action::MOVEMtoMComplete.
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if(mode == 4) {
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offset = 15;
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start_address -= 2;
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write_address_sequence_long(-2, -1, 2, 0);
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movem_final_address_ = start_address;
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} else {
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write_address_sequence_long(2, 1, 0, 2);
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}
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} break;
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case Operation::MOVEMtoMw: {
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setup_movem(1);
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setup_movem(1, movem_writes_steps_);
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if(mode == 4) {
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offset = 15;
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start_address -= 2;
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write_address_sequence_word(-2, -1);
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} else {
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write_address_sequence_word(2, 1);
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}
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} break;
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#undef setup_movem
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#undef write_address_sequence_long
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#undef write_address_sequence_word
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/*
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NEGs: negatives the destination, setting the zero,
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@ -753,6 +792,14 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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}
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} break;
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case int(MicroOp::Action::MOVEMtoMComplete): {
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const auto mode = (decoded_instruction_ >> 3) & 7;
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if(mode == 4) {
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const auto reg = decoded_instruction_ & 7;
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address_[reg] = movem_final_address_;
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}
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} break;
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case int(MicroOp::Action::CopyNextWord):
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next_word_ = prefetch_queue_.halves.low.full;
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break;
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