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https://github.com/TomHarte/CLK.git
synced 2024-12-23 20:29:42 +00:00
Adds some semblance of an AY.
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87a6d22894
commit
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@ -12,8 +12,13 @@
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#include "../../Processors/68000/68000.hpp"
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#include "../../Components/AY38910/AY38910.hpp"
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#include "Video.hpp"
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#include "../../ClockReceiver/JustInTime.hpp"
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#include "../../ClockReceiver/ForceInline.hpp"
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#include "../../Outputs/Speaker/Implementation/LowpassSpeaker.hpp"
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#include "../Utility/MemoryPacker.hpp"
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#include "../Utility/MemoryFuzzer.hpp"
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@ -31,8 +36,11 @@ class ConcreteMachine:
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public CRTMachine::Machine {
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public:
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ConcreteMachine(const Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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mc68000_(*this) {
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mc68000_(*this),
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ay_(audio_queue_),
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speaker_(ay_) {
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set_clock_rate(CLOCK_RATE);
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speaker_.set_input_rate(CLOCK_RATE / 4);
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ram_.resize(512 * 512);
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Memory::Fuzz(ram_);
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@ -58,13 +66,17 @@ class ConcreteMachine:
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memory_map_[0xff] = BusDevice::IO;
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}
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~ConcreteMachine() {
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audio_queue_.flush();
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}
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// MARK: CRTMachine::Machine
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) final {
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video_->set_scan_target(scan_target);
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}
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Outputs::Speaker::Speaker *get_speaker() final {
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return nullptr;
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return &speaker_;
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}
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void run_for(const Cycles cycles) final {
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@ -75,7 +87,7 @@ class ConcreteMachine:
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
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// Advance time.
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video_ += cycle.length;
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advance_time(cycle.length);
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// A null cycle leaves nothing else to do.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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@ -83,6 +95,7 @@ class ConcreteMachine:
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/* TODO: DTack, bus error, VPA. */
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auto address = cycle.word_address();
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if(cycle.data_select_active()) printf("%c %06x\n", (cycle.operation & Microcycle::Read) ? 'r' : 'w', *cycle.address & 0xffffff);
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uint16_t *memory;
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switch(memory_map_[address >> 15]) {
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case BusDevice::MostlyRAM:
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@ -118,11 +131,51 @@ class ConcreteMachine:
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return HalfCycles(0);
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case BusDevice::Unassigned:
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assert(false);
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return HalfCycles(0);
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case BusDevice::IO:
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assert(false);
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break;
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switch(address) {
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default:
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assert(false);
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case 0x7fc000:
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/* Memory controller configuration:
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b0, b1: bank 1
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b2, b3: bank 0
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00 = 128k
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01 = 512k
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10 = 2mb
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11 = reserved
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*/
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break;
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case 0x7fc400: /* PSG: write to select register, read to read register. */
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case 0x7fc401: /* PSG: write to write register. */
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if(!cycle.data_select_active()) return HalfCycles(0);
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// TODO: byte accesses to the odd addresses shouldn't obey logic below.
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advance_time(HalfCycles(2));
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update_audio();
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if(cycle.operation & Microcycle::Read) {
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ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BC2 | GI::AY38910::BC1));
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cycle.value->halves.low = ay_.get_data_output();
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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} else {
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if(address == 0x7fc400) {
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ay_.set_control_lines(GI::AY38910::BC1);
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ay_.set_data_input(cycle.value->halves.low);
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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} else {
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ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BC2 | GI::AY38910::BDIR));
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ay_.set_data_input(cycle.value->halves.low);
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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}
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}
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return HalfCycles(2);
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}
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return HalfCycles(0);
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}
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// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
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@ -150,10 +203,28 @@ class ConcreteMachine:
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return HalfCycles(0);
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}
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void flush() {
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audio_queue_.perform();
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}
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private:
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forceinline void advance_time(HalfCycles length) {
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video_ += length;
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cycles_since_audio_update_ += length;
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}
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void update_audio() {
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speaker_.run_for(audio_queue_, cycles_since_audio_update_.divide_cycles(Cycles(4)));
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}
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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JustInTimeActor<Video, HalfCycles> video_;
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Concurrency::DeferringAsyncTaskQueue audio_queue_;
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GI::AY38910::AY38910 ay_;
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Outputs::Speaker::LowpassSpeaker<GI::AY38910::AY38910> speaker_;
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HalfCycles cycles_since_audio_update_;
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std::vector<uint16_t> ram_;
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std::vector<uint16_t> rom_;
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