Attempt FIRQ, IRQ and NMI responses.
This commit is contained in:
Thomas Harte committed
1 parent
1f6f103346
commit
3d22fe0d1b
1 file changed
+83
-33
+83
-33
@@ -123,19 +123,20 @@ template <typename Traits>
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struct Processor {
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template <Line line>
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void set(const bool value) {
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const auto set_exception = [&](const Exceptions exception) {
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const auto set_exception = [&](const Exception exception) {
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exceptions_ = (exceptions_ & ~exception) | (value ? exception: 0);
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};
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// As below, NMI is edge triggered whereas all the rest are level-triggered.
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switch(line) {
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case Line::PowerOnReset: set_exception(Exceptions::PowerOnReset); break;
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case Line::Reset: set_exception(Exceptions::Reset); break;
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case Line::NMI: set_exception(Exceptions::NMI); break;
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case Line::IRQ: set_exception(Exceptions::IRQ); break;
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case Line::FIRQ: set_exception(Exceptions::FIRQ); break;
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case Line::PowerOnReset: set_exception(Exception::PowerOnReset); break;
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case Line::Reset: set_exception(Exception::Reset); break;
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case Line::NMI: if(value) exceptions_ |= Exception::NMI; break;
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case Line::IRQ: set_exception(Exception::IRQ); break;
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case Line::FIRQ: set_exception(Exception::FIRQ); break;
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case Line::MRDY: mrdy_ = value; break;
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case Line::Halt: set_exception(Exceptions::Halt); break;
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case Line::DMABusReq: dmabreq_ = value; break;
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case Line::Halt: set_exception(Exception::Halt); break;
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case Line::DMABusReq: set_exception(Exception::DMABusReq); break;
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}
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}
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@@ -276,6 +277,15 @@ struct Processor {
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__VA_ARGS__; \
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}
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#define inactive_bus() \
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time_ -= Cycles(1); \
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time_ -= \
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bus_handler_.template perform< \
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BusPhase::FullCycle, \
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ReadWrite::NoData, \
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BusState::HaltOrBusGrantAcknowledge \
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>(Address::Fixed<0xffff>(), Data::NoValue());
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time_ += duration;
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using Literal = Address::Literal;
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@@ -299,27 +309,45 @@ struct Processor {
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reset:
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registers_.dp = 0;
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exceptions_ &= ~(Exceptions::NMI | Exceptions::PowerOnReset);
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exceptions_ &= ~(Exception::NMI | Exception::PowerOnReset);
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registers_.cc.set<ConditionCode::IRQMask>(true);
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registers_.cc.set<ConditionCode::FIRQMask>(true);
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// TODO: spin here on HALT | DMA | BREQ.
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reset_spin:
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if(exceptions_ & (Exception::Halt | Exception::DMABusReq | Exception::Reset)) {
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inactive_bus();
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goto reset_spin;
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}
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read(BusState::InterruptOrResetAcknowledge, Address::Fixed<0xfffe>(), registers_.pc.halves.high);
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read(BusState::InterruptOrResetAcknowledge, Address::Fixed<0xffff>(), registers_.pc.halves.low);
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goto fetch_decode;
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firq:
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registers_.cc.set<ConditionCode::Entire>(false);
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operand_ = registers_.reg<R16::PC>();
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-- registers_.reg<R16::S>();
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write(BusState::Normal, Literal(registers_.reg<R16::S>()), operand_.halves.low);
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-- registers_.reg<R16::S>();
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write(BusState::Normal, Literal(registers_.reg<R16::S>()), operand_.halves.high);
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-- registers_.reg<R16::S>();
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write(BusState::Normal, Literal(registers_.reg<R16::S>()), registers_.reg<R8::CC>());
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registers_.cc.set<ConditionCode::IRQMask>(true);
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registers_.cc.set<ConditionCode::FIRQMask>(true);
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address_.full = 0xfff6;
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read(BusState::Normal, Literal(address_.full), registers_.pc.halves.high, ++address_.full);
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read(BusState::Normal, Literal(address_.full), registers_.pc.halves.low, ++address_.full);
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goto fetch_decode;
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// MARK: - Fetch/decode.
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halt:
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time_ -= Cycles(1);
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time_ -=
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bus_handler_.template perform<
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BusPhase::FullCycle,
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ReadWrite::NoData,
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BusState::HaltOrBusGrantAcknowledge
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>(Address::Fixed<0xffff>(), Data::NoValue());
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inactive_bus();
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fetch_decode:
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case ResumePoint::FetchDecode:
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@@ -329,15 +357,25 @@ struct Processor {
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}
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if(exceptions_) {
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if(exceptions_ & Exceptions::Halt) {
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if(exceptions_ & Exception::Halt) {
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goto halt;
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}
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if(exceptions_ & (Exceptions::PowerOnReset | Exceptions::Reset)) {
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if(exceptions_ & (Exception::PowerOnReset | Exception::Reset)) {
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goto reset;
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}
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// TODO: test interrupts and more.
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if(exceptions_ & Exception::NMI) {
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goto swi_reset_nmi_irq;
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}
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if(exceptions_ & Exception::FIRQ && !registers_.cc.get<ConditionCode::FIRQMask>()) {
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goto firq;
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}
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if(exceptions_ & Exception::IRQ && !registers_.cc.get<ConditionCode::IRQMask>()) {
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goto swi_reset_nmi_irq;
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}
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}
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read(BusState::Normal, Literal(registers_.pc.full), opcode, ++registers_.pc.full);
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@@ -485,7 +523,7 @@ struct Processor {
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case Operation::SWI2:
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case Operation::SWI3:
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case Operation::RESET:
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goto swi;
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goto swi_reset_nmi_irq;
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default: __builtin_unreachable();
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}
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@@ -662,7 +700,7 @@ struct Processor {
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address_.full = registers_.pc.full + operand_.full;
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goto jsr;
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swi:
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swi_reset_nmi_irq:
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if(operation_.operation != Operation::RESET) {
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registers_.cc.set<ConditionCode::Entire>(true);
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}
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@@ -700,16 +738,29 @@ struct Processor {
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-- registers_.reg<R16::S>();
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write(BusState::Normal, Literal(registers_.reg<R16::S>()), registers_.reg<R8::CC>());
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if(operation_.operation == Operation::SWI) {
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if(operation_.operation != Operation::SWI2 && operation_.operation != Operation::SWI2) {
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registers_.cc.set<ConditionCode::IRQMask>(true);
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registers_.cc.set<ConditionCode::FIRQMask>(true);
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address_.full = 0xfffa;
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} else if(operation_.operation == Operation::RESET) {
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address_.full = 0xfffe;
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} else {
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address_.full = operation_.operation == Operation::SWI2 ? 0xfff4 : 0xfff2;
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}
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address_.full = [&]() -> uint16_t {
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if(exceptions_ & Exception::NMI) {
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exceptions_ &= ~Exception::NMI;
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return 0xfffc;
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}
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if(exceptions_ & Exception::IRQ) {
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return 0xfff8;
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}
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switch(operation_.operation) {
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case Operation::SWI: return 0xfffa;
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case Operation::SWI2: return 0xfff4;
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case Operation::SWI3: return 0xfff2;
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default: __builtin_unreachable();
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}
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} ();
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read(BusState::Normal, Literal(address_.full), registers_.pc.halves.high, ++address_.full);
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read(BusState::Normal, Literal(address_.full), registers_.pc.halves.low, ++address_.full);
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goto fetch_decode;
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@@ -776,9 +827,6 @@ private:
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Traits::BusHandlerT &bus_handler_;
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Timescale time_;
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bool mrdy_ = false;
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bool dmabreq_ = false;
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enum ResumePoint {
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FetchDecode,
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Max,
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@@ -791,15 +839,17 @@ private:
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InstructionSet::M6809::OperationReturner::MetaOperation operation_;
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Registers registers_;
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enum Exceptions: uint8_t {
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enum Exception: uint8_t {
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Reset = 1 << 0,
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PowerOnReset = 1 << 1,
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NMI = 1 << 2,
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IRQ = 1 << 3,
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FIRQ = 1 << 4,
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Halt = 1 << 5,
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DMABusReq = 1 << 6, // TODO: implement.
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};
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uint8_t exceptions_ = Exceptions::PowerOnReset;
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uint8_t exceptions_ = Exception::PowerOnReset;
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bool mrdy_ = false;
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// Transient storage.
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Data::Writeable target_;
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