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https://github.com/TomHarte/CLK.git
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The ACIA now receives bits.
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83d73fb088
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@ -89,6 +89,7 @@ void ACIA::write(int address, uint8_t value) {
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transmit.write(false);
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break;
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}
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receive.set_read_delegate(this, Storage::Time(divider_ * 2, receive_clock_rate_.as_int()));
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receive_interrupt_enabled_ = value & 0x80;
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}
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}
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@ -174,3 +175,8 @@ ClockingHint::Preference ACIA::preferred_clocking() {
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bool ACIA::get_interrupt_line() const {
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return interrupt_request_;
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}
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bool ACIA::serial_line_did_produce_bit(Serial::Line *line, int bit) {
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// TODO: how does this affect signalling?
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return false;
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}
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@ -17,7 +17,7 @@
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namespace Motorola {
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namespace ACIA {
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class ACIA: public ClockingHint::Source {
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class ACIA: public ClockingHint::Source, private Serial::Line::ReadDelegate {
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public:
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static constexpr const HalfCycles SameAsTransmit = HalfCycles(0);
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@ -85,6 +85,8 @@ class ACIA: public ClockingHint::Source {
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HalfCycles transmit_clock_rate_;
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HalfCycles receive_clock_rate_;
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bool serial_line_did_produce_bit(Serial::Line *line, int bit) final;
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};
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}
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@ -103,6 +103,7 @@ bool Line::read() {
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void Line::set_read_delegate(ReadDelegate *delegate, Storage::Time bit_length) {
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read_delegate_ = delegate;
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read_delegate_bit_length_ = bit_length;
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read_delegate_bit_length_.simplify();
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write_cycles_since_delegate_call_ = 0;
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}
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