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https://github.com/TomHarte/CLK.git
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The ACIA now receives bits.
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@@ -89,6 +89,7 @@ void ACIA::write(int address, uint8_t value) {
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transmit.write(false);
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break;
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}
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receive.set_read_delegate(this, Storage::Time(divider_ * 2, receive_clock_rate_.as_int()));
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receive_interrupt_enabled_ = value & 0x80;
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}
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}
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@@ -174,3 +175,8 @@ ClockingHint::Preference ACIA::preferred_clocking() {
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bool ACIA::get_interrupt_line() const {
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return interrupt_request_;
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}
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bool ACIA::serial_line_did_produce_bit(Serial::Line *line, int bit) {
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// TODO: how does this affect signalling?
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return false;
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}
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