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Increases quantity of annotations.
I'm now at almost 500 lines, and I haven't even really written anything yet.
This commit is contained in:
Thomas Harte
parent
15bc18b64f
commit
45a391d69e
@ -8,6 +8,7 @@
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#include "z8530.hpp"
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#define LOG_PREFIX "[SCC] "
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#include "../../Outputs/Log.hpp"
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using namespace Zilog::SCC;
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@ -48,7 +49,7 @@ std::uint8_t z8530::read(int address) {
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case 2: // Handled non-symmetrically between channels.
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if(address & 1) {
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LOG("[SCC] Unimplemented: register 2 status bits");
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LOG("Unimplemented: register 2 status bits");
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} else {
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result = interrupt_vector_;
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@ -105,11 +106,11 @@ void z8530::write(int address, std::uint8_t value) {
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case 2: // Interrupt vector register; used only by Channel B.
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// So there's only one of these.
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interrupt_vector_ = value;
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LOG("[SCC] Interrupt vector set to " << PADHEX(2) << int(value));
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LOG("Interrupt vector set to " << PADHEX(2) << int(value));
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break;
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case 9: // Master interrupt and reset register; there is also only one of these.
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LOG("[SCC] Master interrupt and reset register: " << PADHEX(2) << int(value));
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LOG("Master interrupt and reset register: " << PADHEX(2) << int(value));
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master_interrupt_control_ = value;
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break;
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}
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@ -146,16 +147,79 @@ uint8_t z8530::Channel::read(bool data, uint8_t pointer) {
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if(data) {
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return data_;
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} else {
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LOG("Control read from register " << int(pointer));
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// Otherwise, this is a control read...
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switch(pointer) {
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default:
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LOG("[SCC] Unrecognised control read from register " << int(pointer));
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return 0x00;
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case 0:
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case 0x0: // Read Register 0; see p.37 (PDF p.45).
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// b0: Rx character available.
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// b1: zero count.
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// b2: Tx buffer empty.
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// b3: DCD.
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// b4: sync/hunt.
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// b5: CTS.
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// b6: Tx underrun/EOM.
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// b7: break/abort.
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return dcd_ ? 0x8 : 0x0;
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case 0xf:
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case 0x1: // Read Register 1; see p.37 (PDF p.45).
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// b0: all sent.
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// b1: residue code 0.
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// b2: residue code 1.
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// b3: residue code 2.
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// b4: parity error.
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// b5: Rx overrun error.
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// b6: CRC/framing error.
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// b7: end of frame (SDLC).
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return 0x01;
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case 0x2: // Read Register 2; see p.37 (PDF p.45).
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// Interrupt vector — modified by status information in B channel.
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return 0x00;
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case 0x3: // Read Register 3; see p.37 (PDF p.45).
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// B channel: all bits are 0.
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// A channel:
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// b0: Channel B ext/status IP.
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// b1: Channel B Tx IP.
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// b2: Channel B Rx IP.
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// b3: Channel A ext/status IP.
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// b4: Channel A Tx IP.
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// b5: Channel A Rx IP.
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// b6, b7: 0.
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return 0x00;
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case 0xa: // Read Register 10; see p.37 (PDF p.45).
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// b0: 0
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// b1: On loop.
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// b2: 0
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// b3: 0
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// b4: Loop sending.
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// b5: 0
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// b6: Two clocks missing.
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// b7: One clock missing.
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return 0x00;
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case 0xc: // Read Register 12; see p.37 (PDF p.45).
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// Lower byte of time constant.
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return 0x00;
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case 0xd: // Read Register 13; see p.38 (PDF p.46).
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// Upper byte of time constant.
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return 0x00;
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case 0xf: // Read Register 15; see p.38 (PDF p.46).
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// External interrupt status:
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// b0: 0
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// b1: Zero count.
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// b2: 0
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// b3: DCD.
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// b4: Sync/hunt.
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// b5: CTS.
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// b6: Tx underrun/EOM.
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// b7: Break/abort.
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return external_interrupt_status_;
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}
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}
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@ -168,9 +232,10 @@ void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
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data_ = value;
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return;
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} else {
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LOG("Control write: " << PADHEX(2) << int(value) << " to register " << int(pointer));
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switch(pointer) {
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default:
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LOG("[SCC] Unrecognised control write: " << PADHEX(2) << int(value) << " to register " << int(pointer));
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LOG("Unrecognised control write: " << PADHEX(2) << int(value) << " to register " << int(pointer));
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break;
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case 0x0: // Write register 0 — CRC reset and other functions.
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@ -178,13 +243,13 @@ void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
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switch(value >> 6) {
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default: /* Do nothing. */ break;
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case 1:
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LOG("[SCC] TODO: reset Rx CRC checker.");
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LOG("TODO: reset Rx CRC checker.");
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break;
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case 2:
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LOG("[SCC] TODO: reset Tx CRC checker.");
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LOG("TODO: reset Tx CRC checker.");
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break;
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case 3:
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LOG("[SCC] TODO: reset Tx underrun/EOM latch.");
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LOG("TODO: reset Tx underrun/EOM latch.");
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break;
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}
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@ -192,24 +257,24 @@ void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
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switch((value >> 3)&7) {
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default: /* Do nothing. */ break;
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case 2:
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// LOG("[SCC] reset ext/status interrupts.");
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// LOG("reset ext/status interrupts.");
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external_status_interrupt_ = false;
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external_interrupt_status_ = 0;
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break;
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case 3:
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LOG("[SCC] TODO: send abort (SDLC).");
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LOG("TODO: send abort (SDLC).");
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break;
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case 4:
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LOG("[SCC] TODO: enable interrupt on next Rx character.");
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LOG("TODO: enable interrupt on next Rx character.");
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break;
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case 5:
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LOG("[SCC] TODO: reset Tx interrupt pending.");
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LOG("TODO: reset Tx interrupt pending.");
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break;
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case 6:
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LOG("[SCC] TODO: reset error.");
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LOG("TODO: reset error.");
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break;
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case 7:
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LOG("[SCC] TODO: reset highest IUS.");
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LOG("TODO: reset highest IUS.");
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break;
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}
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break;
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@ -234,7 +299,10 @@ void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
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b1 = 1 => transmit buffer empty interrupt is enabled; 0 => it isn't.
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b0 = 1 => external interrupt is enabled; 0 => it isn't.
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*/
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LOG("[SCC] Interrupt mask: " << PADHEX(2) << int(value));
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LOG("Interrupt mask: " << PADHEX(2) << int(value));
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break;
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case 0x2: // Write register 2 - interrupt vector.
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break;
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case 0x3: { // Write register 3 — Receive Parameters and Control.
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@ -246,7 +314,7 @@ void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
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case 2: receive_bit_count = 6; break;
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case 3: receive_bit_count = 8; break;
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}
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LOG("[SCC] Receive bit count: " << receive_bit_count);
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LOG("Receive bit count: " << receive_bit_count);
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/*
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b7,b6:
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@ -259,6 +327,9 @@ void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
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(DCD is ignored in local loopback; CTS is ignored in both auto echo and local loopback).
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b4: enter hunt mode (if set to 1, presumably?)
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b3 = 1 => enable receiver CRC generation; 0 => don't.
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b2: address search mode (SDLC)
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b1: sync character load inhibit.
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b0: Rx enable.
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*/
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} break;
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@ -300,6 +371,23 @@ void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
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}
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break;
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case 0x5:
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// b7: DTR
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// b6/b5:
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// 00 = Tx 5 bits (or less) per character
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// 01 = Tx 7 bits per character
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// 10 = Tx 6 bits per character
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// 11 = Tx 8 bits per character
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// b4: send break.
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// b3: Tx enable.
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// b2: SDLC (if 0) / CRC-16 (if 1)
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// b1: RTS
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// b0: Tx CRC enable.
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break;
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case 0x6:
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break;
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case 0xf: // Write register 15 — External/Status Interrupt Control.
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external_interrupt_mask_ = value;
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break;
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