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https://github.com/TomHarte/CLK.git
synced 2024-11-26 08:49:37 +00:00
At huge copy-and-paste cost, fix MOVE.l.
This commit is contained in:
Thomas Harte
parent
bfd0b683bf
commit
48d51759cd
@ -110,13 +110,6 @@ enum ExecutionState: int {
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Perform_np_n,
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Perform_np_nn,
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MOVE,
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MOVE_predec,
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MOVE_predec_l,
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MOVE_prefetch_decode,
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MOVE_complete,
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MOVE_complete_l,
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TwoOp_Predec_bw,
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TwoOp_Predec_l,
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@ -194,6 +187,7 @@ enum ExecutionState: int {
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MOVE_b, MOVE_w,
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AddressingDispatch(MOVE_bw), MOVE_bw_AbsoluteLong_prefetch_first,
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AddressingDispatch(MOVE_l), MOVE_l_AbsoluteLong_prefetch_first,
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};
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#undef AddressingDispatch
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@ -756,7 +750,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Duplicate(MOVEAw, MOVEw)
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StdCASE(MOVEw, perform_state_ = MOVE_w);
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Duplicate(MOVEAl, MOVEl)
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StdCASE(MOVEl, perform_state_ = MOVE);
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StdCASE(MOVEl, perform_state_ = MOVE_l);
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StdCASE(CMPb, perform_state_ = Perform_np);
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StdCASE(CMPw, perform_state_ = Perform_np);
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@ -1121,6 +1115,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
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MoveToNextOperand(FetchOperand_l);
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BeginStateMode(MOVE_l, AddressRegisterDirect):
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BeginStateMode(MOVE_l, DataRegisterDirect):
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BeginStateMode(MOVE_bw, AddressRegisterDirect):
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registers_[instruction_.reg(1)] = operand_[1];
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Prefetch();
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@ -1160,14 +1156,26 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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MoveToNextOperand(FetchOperand_bw);
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BeginStateMode(MOVE_bw, AddressRegisterIndirect):
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effective_address_[1].l = registers_[8 + instruction_.reg(1)].l;
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SetDataAddress(effective_address_[1].l);
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SetDataAddress(registers_[8 + instruction_.reg(1)].l);
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SetupDataAccess(0, data_select(instruction_));
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, AddressRegisterIndirect):
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effective_address_[1] = registers_[8 + instruction_.reg(1)];
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SetDataAddress(effective_address_[1].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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Access(operand_[next_operand_].high); // nW
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effective_address_[1].l += 2;
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Access(operand_[next_operand_].low); // nW
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(FetchOperand_l, AddressRegisterIndirect):
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effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
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SetDataAddress(effective_address_[next_operand_].l);
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@ -1205,13 +1213,25 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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MoveToNextOperand(FetchOperand_bw);
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BeginStateMode(MOVE_bw, AddressRegisterIndirectWithPostincrement):
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effective_address_[1].l = registers_[8 + instruction_.reg(1)].l;
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SetDataAddress(registers_[8 + instruction_.reg(1)].l);
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SetupDataAccess(0, data_select(instruction_));
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Access(operand_[next_operand_].low); // nw
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registers_[8 + instruction_.reg(next_operand_)].l +=
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address_increments[int(instruction_.operand_size())][instruction_.reg(1)];
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SetDataAddress(effective_address_[1].l);
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SetupDataAccess(0, data_select(instruction_));
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, AddressRegisterIndirectWithPostincrement):
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SetDataAddress(registers_[8 + instruction_.reg(next_operand_)].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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Access(operand_[next_operand_].high); // nW
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registers_[8 + instruction_.reg(next_operand_)].l += 2;
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Access(operand_[next_operand_].low); // nW
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registers_[8 + instruction_.reg(next_operand_)].l += 2;
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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@ -1257,6 +1277,18 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(operand_[next_operand_].low); // nw
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, AddressRegisterIndirectWithPredecrement):
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SetDataAddress(registers_[8 + instruction_.reg(1)].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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Prefetch(); // np
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registers_[8 + instruction_.reg(1)].l -= 2;
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Access(operand_[next_operand_].low); // nw
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registers_[8 + instruction_.reg(1)].l -= 2;
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Access(operand_[next_operand_].high); // nW
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MoveToStateSpecific(Decode);
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BeginStateMode(FetchOperand_l, AddressRegisterIndirectWithPredecrement):
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registers_[8 + instruction_.reg(next_operand_)].l -= 4;
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effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
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@ -1304,6 +1336,21 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, AddressRegisterIndirectWithDisplacement):
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effective_address_[1].l =
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registers_[8 + instruction_.reg(1)].l +
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uint32_t(int16_t(prefetch_.w));
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SetDataAddress(effective_address_[1].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nW
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effective_address_[1].l += 2;
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(FetchOperand_l, AddressRegisterIndirectWithDisplacement):
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effective_address_[next_operand_].l =
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registers_[8 + instruction_.reg(next_operand_)].l +
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@ -1365,6 +1412,21 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, ProgramCounterIndirectWithDisplacement):
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effective_address_[1].l =
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program_counter_.l - 2 +
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uint32_t(int16_t(prefetch_.w));
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SetDataAddress(effective_address_[1].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nW
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effective_address_[1].l += 2;
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(FetchOperand_l, ProgramCounterIndirectWithDisplacement):
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effective_address_[next_operand_].l =
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program_counter_.l - 2 +
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@ -1431,6 +1493,20 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, AddressRegisterIndirectWithIndex8bitDisplacement):
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effective_address_[1].l = d8Xn(registers_[8 + instruction_.reg(1)].l);
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SetDataAddress(effective_address_[1].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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IdleBus(1); // n
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nW
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effective_address_[1].l += 2;
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(FetchOperand_l, AddressRegisterIndirectWithIndex8bitDisplacement):
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effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
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SetDataAddress(effective_address_[next_operand_].l);
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@ -1495,6 +1571,20 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, ProgramCounterIndirectWithIndex8bitDisplacement):
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effective_address_[1].l = d8Xn(program_counter_.l - 2);
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SetDataAddress(effective_address_[1].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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IdleBus(1); // n
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nW
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effective_address_[1].l += 2;
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(FetchOperand_l, ProgramCounterIndirectWithIndex8bitDisplacement):
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effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
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SetDataAddress(effective_address_[next_operand_].l);
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@ -1559,6 +1649,19 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, AbsoluteShort):
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effective_address_[1].l = uint32_t(int16_t(prefetch_.w));
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SetDataAddress(effective_address_[1].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nW
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effective_address_[1].l += 2;
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(FetchOperand_l, AbsoluteShort):
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effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
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SetDataAddress(effective_address_[next_operand_].l);
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@ -1626,6 +1729,38 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(MOVE_l, AbsoluteLong):
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Prefetch(); // np
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effective_address_[1].l = prefetch_.l;
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SetDataAddress(effective_address_[1].l);
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SetupDataAccess(0, Microcycle::SelectWord);
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switch(instruction_.mode(0)) {
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case Mode::AddressRegisterDirect:
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case Mode::DataRegisterDirect:
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case Mode::ImmediateData:
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MoveToStateSpecific(MOVE_l_AbsoluteLong_prefetch_first);
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default: break;
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}
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Access(operand_[next_operand_].high); // nW
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effective_address_[1].l += 2;
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginState(MOVE_l_AbsoluteLong_prefetch_first):
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Prefetch(); // np
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Access(operand_[next_operand_].high); // nW
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effective_address_[1].l += 2;
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Access(operand_[next_operand_].low); // nw
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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BeginStateMode(FetchOperand_l, AbsoluteLong):
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Prefetch(); // np
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@ -1794,107 +1929,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// Specific forms of perform...
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//
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BeginState(MOVE):
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PerformDynamic();
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// In all cases except predecrement mode: do the usual address
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// calculate and storage, then do the next prefetch and decode.
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//
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// In predecrement mode: do the prefetch, then write the result.
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//
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// For here, lump data and address register direct in with predec,
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// so that all that's left is modes that write to memory and then
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// prefetch.
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switch(instruction_.mode(1)) {
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case Mode::DataRegisterDirect: {
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const uint32_t write_mask = size_masks[int(instruction_.operand_size())];
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const int reg = instruction_.reg(1);
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registers_[reg].l =
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(operand_[1].l & write_mask) |
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(registers_[reg].l & ~write_mask);
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}
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MoveToStateSpecific(MOVE_prefetch_decode);
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case Mode::AddressRegisterDirect:
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registers_[8 + instruction_.reg(1)].l = operand_[1].l;
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MoveToStateSpecific(MOVE_prefetch_decode);
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case Mode::AddressRegisterIndirectWithPredecrement:
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MoveToStateSpecific(MOVE_predec);
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default: break;
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}
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next_operand_ = 1;
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post_ea_state_ = MOVE_complete;
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MoveToStateSpecific(CalcEffectiveAddress);
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BeginState(MOVE_prefetch_decode):
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Prefetch();
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MoveToStateSpecific(Decode);
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BeginState(MOVE_predec):
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Prefetch();
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SetDataAddress(registers_[8 + instruction_.reg(1)].l);
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switch(instruction_.operand_size()) {
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case InstructionSet::M68k::DataSize::LongWord:
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MoveToStateSpecific(MOVE_predec_l);
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case InstructionSet::M68k::DataSize::Word:
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SetupDataAccess(0, Microcycle::SelectWord);
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registers_[8 + instruction_.reg(1)].l -= 2;
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break;
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case InstructionSet::M68k::DataSize::Byte:
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SetupDataAccess(0, Microcycle::SelectByte);
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registers_[8 + instruction_.reg(1)].l -=
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address_increments[0][instruction_.reg(next_operand_)];
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break;
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}
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SetDataAddress(registers_[8 + instruction_.reg(1)].l);
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Access(operand_[1].low);
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MoveToStateSpecific(Decode);
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BeginState(MOVE_predec_l):
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SetupDataAccess(0, Microcycle::SelectWord);
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registers_[8 + instruction_.reg(1)].l -= 2;
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Access(operand_[1].low);
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registers_[8 + instruction_.reg(1)].l -= 2;
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Access(operand_[1].high);
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MoveToStateSpecific(Decode);
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BeginState(MOVE_complete):
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SetDataAddress(effective_address_[1].l);
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switch(instruction_.operand_size()) {
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case InstructionSet::M68k::DataSize::LongWord:
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SetupDataAccess(0, Microcycle::SelectWord);
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MoveToStateSpecific(MOVE_complete_l);
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case InstructionSet::M68k::DataSize::Word:
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SetupDataAccess(0, Microcycle::SelectWord);
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break;
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case InstructionSet::M68k::DataSize::Byte:
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SetupDataAccess(0, Microcycle::SelectByte);
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break;
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}
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Access(operand_[1].low);
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Prefetch();
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MoveToStateSpecific(Decode);
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BeginState(MOVE_complete_l):
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Access(operand_[1].high);
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effective_address_[1].l += 2;
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Access(operand_[1].low);
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Prefetch();
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MoveToStateSpecific(Decode);
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//
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// MOVE
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//
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BeginState(MOVE_b):
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PerformSpecific(MOVEb);
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MoveToAddressingMode(MOVE_bw, instruction_.mode(1));
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@ -1903,6 +1940,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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PerformSpecific(MOVEw);
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MoveToAddressingMode(MOVE_bw, instruction_.mode(1));
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BeginState(MOVE_l):
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PerformSpecific(MOVEl);
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MoveToAddressingMode(MOVE_l, instruction_.mode(1));
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//
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// [ABCD/SBCD/SUBX/ADDX] (An)-, (An)-
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//
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