6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-22 12:33:29 +00:00
Code Issues Projects Releases Wiki Activity

Takes a run at TRAPV.

Browse Source 
... to leave 1466 as the unimplemented count.
This commit is contained in:
Thomas Harte 2019-04-28 15:52:58 -04:00
parent 8e8dce9bec
commit 4b1324de77
3 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -953,6 +953,16 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
program_counter_.full -= 2;
} break;
case Operation::TRAPV: {
if(overflow_flag_) {
// Select the trap steps as next; the initial microcycle should be 4 cycles long.
bus_program = trap_steps_;
bus_program->microcycle.length = HalfCycles(0);
populate_trap_steps(7, get_status());
program_counter_.full -= 4;
}
} break;
case Operation::CHK: {
const bool is_under = int16_t(active_program_->destination->halves.low.full) < 0;
const bool is_over = int16_t(active_program_->destination->halves.low.full) > int16_t(active_program_->source->halves.low.full);

8
Processors/68000/Implementation/68000Storage.cpp
View File

@ -447,6 +447,7 @@ struct ProcessorStorageConstructor {
MOVEUSP, // Maps a direction and register to a MOVE [to/from] USP.
TRAP, // Maps to a TRAP.
TRAPV, // Maps to a TRAPV.
CHK, // Maps to a CHK.
NOP, // Maps to a NOP.
@ -665,6 +666,7 @@ struct ProcessorStorageConstructor {
{0xfff0, 0x4e60, Operation::MOVEAl, Decoder::MOVEUSP}, // 6-21 (p475)
{0xfff0, 0x4e40, Operation::TRAP, Decoder::TRAP}, // 4-188 (p292)
{0xffff, 0x4e76, Operation::TRAPV, Decoder::TRAPV}, // 4-191 (p295)
{0xf1c0, 0x4180, Operation::CHK, Decoder::CHK}, // 4-69 (p173)
{0xffff, 0x4e77, Operation::RTE_RTR, Decoder::RTE_RTR}, // 4-168 (p272) [RTR]
@ -3213,6 +3215,12 @@ struct ProcessorStorageConstructor {
op();
} break;
case Decoder::TRAPV: {
op(Action::None, seq("np"));
op(Action::PerformOperation);
op();
} break;
case Decoder::CHK: {
storage_.instructions[instruction].set_destination(storage_, Dn, data_register);
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);

2
Processors/68000/Implementation/68000Storage.hpp
View File

@ -104,7 +104,7 @@ class ProcessorStorage {
RTE_RTR,
TRAP,
TRAP, TRAPV,
CHK,
EXG, SWAP,