Tweak again.
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@@ -40,7 +40,7 @@ CD90_640::CD90_640() : WD::WD1770(P1770) {
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// ;
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// a2a1 LDY #M09C4 ; 4 µs
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// a2a5 DEY ; 4 µs
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// a2a7 BNE ZA2A5 ; 3 µs = net delay of 4 + 9C4*7 = 17,500 µs
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// a2a7 BNE ZA2A5 ; 3 µs = net delay of 4 + 9C4*7 = 17,504 µs
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//
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// a2a9 PSHS CC ; 6 µs
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// a2ab SEIF ; 3 µs
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@@ -68,7 +68,7 @@ CD90_640::CD90_640() : WD::WD1770(P1770) {
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// If I've disassembled that correctly, then the process is:
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//
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// (1) wait for index hole, with up to 9 µs of latency;
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// (2) spin in a loop for 17,500 µs;
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// (2) spin in a loop for 17,504 µs;
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// (3) do minor stack/flag work for 9 µs;
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// (4) count time from here until next index hole, ending with Y = time/13;
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// (5) test that that is within the bounds 0x311b, 0x3357.
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@@ -76,18 +76,18 @@ CD90_640::CD90_640() : WD::WD1770(P1770) {
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// Ignoring minor potential latencies in loop exits, that's:
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//
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// (1) wait for index hole;
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// (2) spend 17,509 µs doing something else;
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// (2) spend 17,513 µs doing something else;
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// (3) get Y = [µs from there to next index hole] / 13.
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//
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// i.e. it's a test that the rotation it samples takes n µs, where:
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//
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// 13 * 0x311b < n - 17,509 < 13 * 0x3357
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// 13 * 12,571 + 17,509 < n < 13 * 13,143 + 17,509
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// 180,932 < n < 188,368
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// 13 * 0x311b < n - 17,513 < 13 * 0x3357
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// 13 * 12,571 + 17,513 < n < 13 * 13,143 + 17,513
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// 180,936 < n < 188,372
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//
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// i.e.
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//
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// 331 >= RPM >= 319 RPM.
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// ~331 >= RPM >= ~319 RPM.
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//
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// So 325 RPM is a really weird number but I can't currently say why it should be
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// wrong rather than merely unexpected. So here it is.
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