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Fully implement TAS.

This commit is contained in:
Thomas Harte 2022-05-22 16:14:03 -04:00
parent 1dd6ed6ae3
commit 4e34727195
3 changed files with 34 additions and 3 deletions

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@ -188,7 +188,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
// @"rts.json",
@"swap.json",
@"tas.json",
// @"tst.json",
@"tst.json",
]];
// _testSet = [NSSet setWithArray:@[@"TAS 4ac0"]];
}

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@ -1921,9 +1921,31 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// TAS
//
BeginState(TAS):
// Populate all addresses.
tas_cycles[0].address = tas_cycles[1].address =
tas_cycles[2].address =
tas_cycles[3].address = tas_cycles[4].address = &effective_address_[0].l;
// TODO: use the specialised TAS bus cycle; five parts.
// PerformBusOperation
// Populate values to the relevant subset.
tas_cycles[0].value = tas_cycles[1].value =
tas_cycles[3].value = tas_cycles[4].value = &operand_[0].low;
// First two parts: the read.
PerformBusOperation(tas_cycles[0]);
PerformBusOperation(tas_cycles[1]);
// Third part: processing time.
PerformBusOperation(tas_cycles[2]);
// Do the actual TAS operation.
status_.overflow_flag = status_.carry_flag = 0;
status_.zero_result = operand_[0].b;
status_.negative_flag = operand_[0].b & 0x80;
// Final parts: write back.
operand_[0].b |= 0x80;
PerformBusOperation(tas_cycles[3]);
PerformBusOperation(tas_cycles[4]);
Prefetch();
MoveToStateSpecific(Decode);

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@ -176,6 +176,15 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsData
};
// TAS.
Microcycle tas_cycles[5] = {
{ Microcycle::Read | Microcycle::NewAddress | Microcycle::IsData },
{ Microcycle::Read | Microcycle::SameAddress | Microcycle::IsData | Microcycle::SelectByte },
{ Microcycle::SameAddress },
{ Microcycle::SameAddress | Microcycle::IsData },
{ Microcycle::SameAddress | Microcycle::IsData | Microcycle::SelectByte },
};
// Holding spot when awaiting DTACK/etc.
Microcycle awaiting_dtack;
};