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Edges towards offering the 65816 as another type of 6502 for testing.
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@ -15,7 +15,7 @@ class MOS6502InterruptTests: XCTestCase {
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super.setUp()
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// create a machine full of NOPs
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machine = CSTestMachine6502(is65C02: false)
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machine = CSTestMachine6502(processor: .processor6502)
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for c in 0...65535 {
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machine.setValue(0xea, forAddress: UInt16(c))
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}
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@ -12,7 +12,7 @@ import XCTest
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class MOS6502TimingTests: XCTestCase, CSTestMachineTrapHandler {
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private var endTime: UInt32 = 0
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private let machine = CSTestMachine6502(is65C02: false)
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private let machine = CSTestMachine6502(processor: .processor6502)
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func testImplied() {
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let code: [UInt8] = [
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@ -13,7 +13,7 @@ class AllSuiteATests: XCTestCase {
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func testAllSuiteA() {
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if let filename = Bundle(for: type(of: self)).path(forResource: "AllSuiteA", ofType: "bin") {
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if let allSuiteA = try? Data(contentsOf: URL(fileURLWithPath: filename)) {
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let machine = CSTestMachine6502(is65C02: false)
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let machine = CSTestMachine6502(processor: .processor6502)
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machine.setData(allSuiteA, atAddress: 0x4000)
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machine.setValue(CSTestMachine6502JamOpcode, forAddress:0x45c0); // end
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@ -14,7 +14,7 @@ class BCDTest: XCTestCase, CSTestMachineTrapHandler {
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func testBCD() {
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if let filename = Bundle(for: type(of: self)).path(forResource: "BCDTEST_beeb", ofType: nil) {
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if let bcdTest = try? Data(contentsOf: URL(fileURLWithPath: filename)) {
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let machine = CSTestMachine6502(is65C02: false)
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let machine = CSTestMachine6502(processor: .processor6502)
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machine.trapHandler = self
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machine.setData(bcdTest, atAddress: 0x2900)
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@ -19,13 +19,19 @@ typedef NS_ENUM(NSInteger, CSTestMachine6502Register) {
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CSTestMachine6502RegisterY,
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};
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typedef NS_ENUM(NSInteger, CSTestMachine6502Processor) {
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CSTestMachine6502Processor6502,
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CSTestMachine6502Processor65C02,
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CSTestMachine6502Processor65816
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};
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extern const uint8_t CSTestMachine6502JamOpcode;
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@interface CSTestMachine6502 : CSTestMachine
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- (nonnull instancetype)init NS_UNAVAILABLE;
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- (nonnull instancetype)initIs65C02:(BOOL)is65C02;
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- (nonnull instancetype)initWithProcessor:(CSTestMachine6502Processor)processor;
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- (void)setData:(nonnull NSData *)data atAddress:(uint16_t)startAddress;
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- (void)runForNumberOfCycles:(int)cycles;
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@ -9,6 +9,7 @@
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#import "TestMachine6502.h"
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#include <stdint.h>
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#include "../../../../Processors/6502/AllRAM/6502AllRAM.hpp"
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//#include "../../../../Processors/65816/AllRAM/65816AllRAM.hpp"
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#import "TestMachine+ForSubclassEyesOnly.h"
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const uint8_t CSTestMachine6502JamOpcode = CPU::MOS6502::JamOpcode;
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@ -35,12 +36,21 @@ static CPU::MOS6502::Register registerForRegister(CSTestMachine6502Register reg)
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#pragma mark - Lifecycle
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- (instancetype)initIs65C02:(BOOL)is65C02 {
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- (instancetype)initWithProcessor:(CSTestMachine6502Processor)processor {
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self = [super init];
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if(self) {
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_processor = CPU::MOS6502::AllRAMProcessor::Processor(
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is65C02 ? CPU::MOS6502::Personality::PWDC65C02 : CPU::MOS6502::Personality::P6502);
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switch(processor) {
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case CSTestMachine6502Processor6502:
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_processor = CPU::MOS6502::AllRAMProcessor::Processor(CPU::MOS6502::Personality::P6502);
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break;
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case CSTestMachine6502Processor65C02:
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_processor = CPU::MOS6502::AllRAMProcessor::Processor(CPU::MOS6502::Personality::PWDC65C02);
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break;
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default:
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assert(false); // TODO
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}
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}
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return self;
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@ -23,7 +23,7 @@ class BusOperationHandler: public CPU::Z80::AllRAMProcessor::MemoryAccessDelegat
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public:
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BusOperationHandler(CSTestMachineZ80 *targetMachine) : target_(targetMachine) {}
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void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, HalfCycles time_stamp) {
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void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &, CPU::Z80::PartialMachineCycle::Operation operation, uint16_t address, uint8_t value, HalfCycles time_stamp) {
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[target_ testMachineDidPerformBusOperation:operation address:address value:value timeStamp:time_stamp];
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}
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@ -77,7 +77,7 @@ struct PortAccessDelegateTopByte: public CPU::Z80::AllRAMProcessor::PortAccessDe
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};
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struct PortAccessDelegate191: public CPU::Z80::AllRAMProcessor::PortAccessDelegate {
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uint8_t z80_all_ram_processor_input(uint16_t port) final { return 191; }
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uint8_t z80_all_ram_processor_input(uint16_t) final { return 191; }
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};
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#pragma mark - Capture class
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@ -23,7 +23,7 @@ class ComparativeBusHandler: public CPU::MC68000::BusHandler {
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gzclose(trace);
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}
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void will_perform(uint32_t address, uint16_t opcode) {
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void will_perform(uint32_t address, uint16_t) {
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// Obtain the next line from the trace file.
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char correct_state[300] = "\n";
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gzgets(trace, correct_state, sizeof(correct_state));
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@ -45,7 +45,7 @@ class ComparativeBusHandler: public CPU::MC68000::BusHandler {
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fprintf(stderr, "Diverges at line %d\n", line_count);
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fprintf(stderr, "Good: %s", correct_state);
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fprintf(stderr, "Bad: %s", local_state);
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assert(false);
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throw std::exception();
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}
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}
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@ -14,7 +14,7 @@ class KlausDormannTests: XCTestCase {
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fileprivate func runTest(resource: String, is65C02: Bool) -> UInt16 {
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if let filename = Bundle(for: type(of: self)).path(forResource: resource, ofType: "bin") {
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if let functionalTest = try? Data(contentsOf: URL(fileURLWithPath: filename)) {
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let machine = CSTestMachine6502(is65C02: is65C02)
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let machine = CSTestMachine6502(processor: is65C02 ? .processor65C02 : .processor6502)
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machine.setData(functionalTest, atAddress: 0)
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machine.setValue(0x400, for: .programCounter)
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@ -200,7 +200,7 @@ class WolfgangLorenzTests: XCTestCase, CSTestMachineTrapHandler {
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if let filename = Bundle(for: type(of: self)).path(forResource: name, ofType: nil) {
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if let testData = try? Data(contentsOf: URL(fileURLWithPath: filename)) {
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machine = CSTestMachine6502(is65C02: false)
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machine = CSTestMachine6502(processor: .processor6502)
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machine.trapHandler = self
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// machine.logActivity = true
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output = ""
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@ -699,9 +699,6 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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}
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};
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// TEMPORARY. Kneejerk way to get a step debug of 65816 storage construction.
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ProcessorStorage TEMPORARY_test_instance;
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ProcessorStorage::ProcessorStorage() {
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ProcessorStorageConstructor constructor(*this);
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