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Corrected non-default refresh cycle lengths. Reduces failures of the currently-tested timing subset from 10 to 4.

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This commit is contained in:
Thomas Harte 2017-06-19 07:34:23 -04:00
parent 85c5c4405a
commit 54e4643396
1 changed files with 1 additions and 1 deletions
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Processors/Z80/Z80.hpp
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@ -86,7 +86,7 @@ struct MachineCycle {
// Elemental bus operations
#define ReadOpcodeStart(addr, val) {MachineCycle::ReadOpcode, MachineCycle::Phase::Start, 2, &addr.full, &val, false}
#define ReadOpcodeWait(addr, val) {MachineCycle::ReadOpcode, MachineCycle::Phase::Wait, 1, &addr.full, &val, true}
#define Refresh(len) {MachineCycle::Refresh, MachineCycle::Phase::End, 2, &ir_.full, nullptr, false}
#define Refresh(len) {MachineCycle::Refresh, MachineCycle::Phase::End, len, &ir_.full, nullptr, false}
#define ReadStart(addr, val) {MachineCycle::Read, MachineCycle::Phase::Start, 2, &addr.full, &val, false}
#define ReadWait(l, addr, val, f) {MachineCycle::Read, MachineCycle::Phase::Wait, l, &addr.full, &val, f}