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Correct timing of ADDQ.

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This commit is contained in:
Thomas Harte 2022-05-29 14:34:06 -04:00
parent 35e73b77f4
commit 57aa8d2f17
1 changed files with 18 additions and 11 deletions
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29
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -747,18 +747,25 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Duplicate(SUBb, ADDb) StdCASE(ADDb, perform_state_ = Perform_np)
Duplicate(SUBw, ADDw) StdCASE(ADDw, perform_state_ = Perform_np)
Duplicate(SUBl, ADDl) StdCASE(ADDl, {
if(instruction_.mode(1) != Mode::DataRegisterDirect) {
perform_state_ = Perform_np;
if(instruction_.mode(0) == Mode::Quick) {
perform_state_ = (
instruction_.mode(1) == Mode::AddressRegisterDirect ||
instruction_.mode(1) == Mode::DataRegisterDirect
) ? Perform_np_nn : Perform_np;
} else {
switch(instruction_.mode(0)) {
default:
perform_state_ = Perform_np_n;
break;
case Mode::DataRegisterDirect:
case Mode::AddressRegisterDirect:
case Mode::ImmediateData:
perform_state_ = Perform_np_nn;
break;
if(instruction_.mode(1) != Mode::DataRegisterDirect) {
perform_state_ = Perform_np;
} else {
switch(instruction_.mode(0)) {
default:
perform_state_ = Perform_np_n;
break;
case Mode::DataRegisterDirect:
case Mode::AddressRegisterDirect:
case Mode::ImmediateData:
perform_state_ = Perform_np_nn;
break;
}
}
}
})