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Implements PLX, PLY, PHX and PHY.

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This commit is contained in:
Thomas Harte 2018-08-06 22:00:23 -04:00
parent 1a44ef0469
commit 5c881bd19d
3 changed files with 20 additions and 4 deletions
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6
Processors/6502/Implementation/6502Implementation.hpp
View File

@ -115,6 +115,8 @@ if(number_of_cycles <= Cycles(0)) break;
case CyclePushPCL: push(pc_.bytes.low); break; case CyclePushPCL: push(pc_.bytes.low); break;
case CyclePushOperand: push(operand_); break; case CyclePushOperand: push(operand_); break;
case CyclePushA: push(a_); break; case CyclePushA: push(a_); break;
case CyclePushX: push(x_); break;
case CyclePushY: push(y_); break;
case CycleNoWritePush: { case CycleNoWritePush: {
uint16_t targetAddress = s_ | 0x100; s_--; uint16_t targetAddress = s_ | 0x100; s_--;
read_mem(operand_, targetAddress); read_mem(operand_, targetAddress);
@ -140,11 +142,15 @@ if(number_of_cycles <= Cycles(0)) break;
case CyclePullPCL: s_++; read_mem(pc_.bytes.low, s_ | 0x100); break; case CyclePullPCL: s_++; read_mem(pc_.bytes.low, s_ | 0x100); break;
case CyclePullPCH: s_++; read_mem(pc_.bytes.high, s_ | 0x100); break; case CyclePullPCH: s_++; read_mem(pc_.bytes.high, s_ | 0x100); break;
case CyclePullA: s_++; read_mem(a_, s_ | 0x100); break; case CyclePullA: s_++; read_mem(a_, s_ | 0x100); break;
case CyclePullX: s_++; read_mem(x_, s_ | 0x100); break;
case CyclePullY: s_++; read_mem(y_, s_ | 0x100); break;
case CyclePullOperand: s_++; read_mem(operand_, s_ | 0x100); break; case CyclePullOperand: s_++; read_mem(operand_, s_ | 0x100); break;
case OperationSetFlagsFromOperand: set_flags(operand_); continue; case OperationSetFlagsFromOperand: set_flags(operand_); continue;
case OperationSetOperandFromFlagsWithBRKSet: operand_ = get_flags() | Flag::Break; continue; case OperationSetOperandFromFlagsWithBRKSet: operand_ = get_flags() | Flag::Break; continue;
case OperationSetOperandFromFlags: operand_ = get_flags(); continue; case OperationSetOperandFromFlags: operand_ = get_flags(); continue;
case OperationSetFlagsFromA: zero_result_ = negative_result_ = a_; continue; case OperationSetFlagsFromA: zero_result_ = negative_result_ = a_; continue;
case OperationSetFlagsFromX: zero_result_ = negative_result_ = x_; continue;
case OperationSetFlagsFromY: zero_result_ = negative_result_ = y_; continue;
case CycleIncrementPCAndReadStack: pc_.full++; throwaway_read(s_ | 0x100); break; case CycleIncrementPCAndReadStack: pc_.full++; throwaway_read(s_ | 0x100); break;
case CycleReadPCLFromAddress: read_mem(pc_.bytes.low, address_.full); break; case CycleReadPCLFromAddress: read_mem(pc_.bytes.low, address_.full); break;

13
Processors/6502/Implementation/6502Storage.cpp
View File

@ -218,8 +218,17 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
memcpy(operations_, operations_6502, sizeof(operations_)); memcpy(operations_, operations_6502, sizeof(operations_));
// Patch the table according to the chip's personality. // Patch the table according to the chip's personality.
switch(personality) { if(personality != P6502) {
default: break; // This is a 65C02 or 65SC02; add P[L/H][X/Y]
const ProcessorStorage::MicroOp phx[10] = Program(CyclePushX);
const ProcessorStorage::MicroOp phy[10] = Program(CyclePushY);
const ProcessorStorage::MicroOp plx[10] = Program(CycleReadFromS, CyclePullX, OperationSetFlagsFromX);
const ProcessorStorage::MicroOp ply[10] = Program(CycleReadFromS, CyclePullY, OperationSetFlagsFromY);
memcpy(&operations_[0x5a], phy, sizeof(phy));
memcpy(&operations_[0xda], phx, sizeof(phx));
memcpy(&operations_[0x7a], ply, sizeof(ply));
memcpy(&operations_[0xfa], plx, sizeof(plx));
} }
} }

5
Processors/6502/Implementation/6502Storage.hpp
View File

@ -25,13 +25,14 @@ class ProcessorStorage {
enum MicroOp { enum MicroOp {
CycleFetchOperation, CycleFetchOperand, OperationDecodeOperation, CycleIncPCPushPCH, CycleFetchOperation, CycleFetchOperand, OperationDecodeOperation, CycleIncPCPushPCH,
CyclePushPCH, CyclePushPCL, CyclePushA, CyclePushOperand, CyclePushPCH, CyclePushPCL, CyclePushA, CyclePushOperand,
OperationSetI, CyclePushX, CyclePushY, OperationSetI,
OperationBRKPickVector, OperationNMIPickVector, OperationRSTPickVector, OperationBRKPickVector, OperationNMIPickVector, OperationRSTPickVector,
CycleReadVectorLow, CycleReadVectorHigh, CycleReadVectorLow, CycleReadVectorHigh,
CycleReadFromS, CycleReadFromPC, CycleReadFromS, CycleReadFromPC,
CyclePullOperand, CyclePullPCL, CyclePullPCH, CyclePullA, CyclePullOperand, CyclePullPCL, CyclePullPCH, CyclePullA,
CyclePullX, CyclePullY,
CycleNoWritePush, CycleNoWritePush,
CycleReadAndIncrementPC, CycleIncrementPCAndReadStack, CycleIncrementPCReadPCHLoadPCL, CycleReadPCHLoadPCL, CycleReadAndIncrementPC, CycleIncrementPCAndReadStack, CycleIncrementPCReadPCHLoadPCL, CycleReadPCHLoadPCL,
CycleReadAddressHLoadAddressL, CycleReadPCLFromAddress, CycleReadPCHFromAddress, CycleLoadAddressAbsolute, CycleReadAddressHLoadAddressL, CycleReadPCLFromAddress, CycleReadPCHFromAddress, CycleLoadAddressAbsolute,
@ -58,7 +59,7 @@ class ProcessorStorage {
OperationSBX, OperationLXA, OperationANE, OperationANC, OperationSBX, OperationLXA, OperationANE, OperationANC,
OperationLAS, CycleAddSignedOperandToPC, OperationSetFlagsFromOperand, OperationSetOperandFromFlagsWithBRKSet, OperationLAS, CycleAddSignedOperandToPC, OperationSetFlagsFromOperand, OperationSetOperandFromFlagsWithBRKSet,
OperationSetOperandFromFlags, OperationSetOperandFromFlags,
OperationSetFlagsFromA, OperationSetFlagsFromA, OperationSetFlagsFromX, OperationSetFlagsFromY,
CycleScheduleJam CycleScheduleJam
}; };