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Correct test logic.

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All tests now pass.
This commit is contained in:
Thomas Harte 2021-11-25 04:11:20 -05:00
parent 012084b37b
commit 610c85a354
1 changed files with 22 additions and 4 deletions
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26
OSBindings/Mac/Clock SignalTests/AmigaBlitterTests.mm
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@ -10,6 +10,7 @@
#include "Blitter.hpp" #include "Blitter.hpp"
#include <unordered_map>
#include <vector> #include <vector>
namespace Amiga { namespace Amiga {
@ -37,14 +38,29 @@ using WriteVector = std::vector<std::pair<uint32_t, uint16_t>>;
@implementation AmigaBlitterTests @implementation AmigaBlitterTests
- (BOOL)verifyWrites:(WriteVector &)writes blitter:(Amiga::Blitter &)blitter ram:(uint16_t *)ram { - (BOOL)verifyWrites:(WriteVector &)writes blitter:(Amiga::Blitter &)blitter ram:(uint16_t *)ram approximateLocation:(NSInteger)approximateLocation {
// Run for however much time the Blitter wants. // Run for however much time the Blitter wants.
while(blitter.get_status() & 0x4000) { while(blitter.get_status() & 0x4000) {
blitter.advance_dma(); blitter.advance_dma();
} }
// Some blits will write the same address twice
// (e.g. by virtue of an appropriate modulo), but
// this unit test is currently able to verify the
// final result only. So count number of accesses per
// address up front in order only to count the
// final ones below.
std::unordered_map<int, int> access_counts;
for(const auto &write: writes) { for(const auto &write: writes) {
XCTAssertEqual(ram[write.first >> 1], write.second, @"Didn't find %04x at address %08x; found %04x instead", write.second, write.first, ram[write.first >> 1]); ++access_counts[write.first];
}
for(const auto &write: writes) {
auto &count = access_counts[write.first];
--count;
if(count) continue;
XCTAssertEqual(ram[write.first >> 1], write.second, @"Didn't find %04x at address %08x; found %04x instead, somewhere before line %ld", write.second, write.first, ram[write.first >> 1], (long)approximateLocation);
// For now, indicate only the first failure. // For now, indicate only the first failure.
if(ram[write.first >> 1] != write.second) { if(ram[write.first >> 1] != write.second) {
@ -80,7 +96,9 @@ using WriteVector = std::vector<std::pair<uint32_t, uint16_t>>;
WriteVector writes; WriteVector writes;
BOOL hasFailed = NO; BOOL hasFailed = NO;
NSInteger arrayEntry = -1;
for(NSArray *const event in trace) { for(NSArray *const event in trace) {
++arrayEntry;
if(hasFailed) break; if(hasFailed) break;
NSString *const type = event[0]; NSString *const type = event[0];
@ -106,7 +124,7 @@ using WriteVector = std::vector<std::pair<uint32_t, uint16_t>>;
// Hackaround for testing my magical all-at-once Blitter is here. // Hackaround for testing my magical all-at-once Blitter is here.
if(state == State::LoggingWrites) { if(state == State::LoggingWrites) {
if(![self verifyWrites:writes blitter:blitter ram:ram]) { if(![self verifyWrites:writes blitter:blitter ram:ram approximateLocation:arrayEntry]) {
hasFailed = YES; hasFailed = YES;
break; break;
} }
@ -209,7 +227,7 @@ using WriteVector = std::vector<std::pair<uint32_t, uint16_t>>;
// Check the final set of writes. // Check the final set of writes.
if(!hasFailed) { if(!hasFailed) {
[self verifyWrites:writes blitter:blitter ram:ram]; [self verifyWrites:writes blitter:blitter ram:ram approximateLocation:-1];
} }
} }