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Adds sufficient address decoding to print a more helpful exit message.

This commit is contained in:
Thomas Harte 2021-07-18 12:13:56 -04:00
parent 48999c03a5
commit 622cca0acf
2 changed files with 35 additions and 17 deletions

View File

@ -9,18 +9,24 @@
#ifndef _526Implementation_h #ifndef _526Implementation_h
#define _526Implementation_h #define _526Implementation_h
#include <cassert>
#include <cstdio>
namespace MOS { namespace MOS {
namespace MOS6526 { namespace MOS6526 {
template <typename BusHandlerT, Personality personality> template <typename BusHandlerT, Personality personality>
void MOS6526<BusHandlerT, personality>::write(int address, uint8_t value) { void MOS6526<BusHandlerT, personality>::write(int address, uint8_t value) {
(void)address; address &= 0xf;
(void)value; printf("Unhandled 6526 write: %02x to %d\n", value, address);
assert(false);
} }
template <typename BusHandlerT, Personality personality> template <typename BusHandlerT, Personality personality>
uint8_t MOS6526<BusHandlerT, personality>::read(int address) { uint8_t MOS6526<BusHandlerT, personality>::read(int address) {
(void)address; address &= 0xf;
printf("Unhandled 6526 read from %d\n", address);
assert(false);
return 0xff; return 0xff;
} }

View File

@ -29,8 +29,8 @@ class ConcreteMachine:
public: public:
ConcreteMachine(const Analyser::Static::Amiga::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) : ConcreteMachine(const Analyser::Static::Amiga::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
mc68000_(*this), mc68000_(*this),
cia1_(cia1_handler_), cia_a_(cia_a_handler_),
cia2_(cia2_handler_) cia_b_(cia_b_handler_)
{ {
(void)target; (void)target;
@ -77,8 +77,8 @@ class ConcreteMachine:
// (or at least enqueue them, JIT-wise). // (or at least enqueue them, JIT-wise).
// Advance time. // Advance time.
cia1_.run_for(cycle.length); cia_a_.run_for(cycle.length);
cia2_.run_for(cycle.length); cia_b_.run_for(cycle.length);
// Do nothing if no address is exposed. // Do nothing if no address is exposed.
if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0); if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
@ -88,15 +88,27 @@ class ConcreteMachine:
// Grab the target address to pick a memory source. // Grab the target address to pick a memory source.
const uint32_t address = cycle.host_endian_byte_address(); const uint32_t address = cycle.host_endian_byte_address();
if(cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord)) { if(cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord)) {
printf("%06x\n", address); printf("%06x\n", *cycle.address);
} }
if(!regions_[address >> 18].read_write_mask) { if(!regions_[address >> 18].read_write_mask) {
if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) { if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) {
// Check for various potential chip accesses. // Check for various potential chip accesses.
if(address >= 0xbf'd000 && address <= 0xbf'ef01) {
printf("Unimplemented CIA %06x\n", address); // CIA A is: 101x xxxx xx01 rrrr xxxx xxx0 (i.e. loaded into high byte)
assert(false); // CIA B is: 101x xxxx xx10 rrrr xxxx xxx1 (i.e. loaded into low byte)
if((address & 0xe0'0000) == 0xa0'0000) {
const int reg = address >> 8;
if(cycle.operation & Microcycle::Read) {
uint16_t result = 0xffff;
if(address & 0x1000) result &= 0x00ff | (cia_a_.read(reg) << 8);
if(address & 0x2000) result &= 0xff00 | (cia_b_.read(reg) << 0);
cycle.set_value16(result);
} else {
if(address & 0x1000) cia_a_.write(reg, cycle.value8_high());
if(address & 0x2000) cia_b_.write(reg, cycle.value8_low());
}
} else if(address >= 0xdf'f000 && address <= 0xdf'f1be) { } else if(address >= 0xdf'f000 && address <= 0xdf'f1be) {
printf("Unimplemented chipset access %06x\n", address); printf("Unimplemented chipset access %06x\n", address);
assert(false); assert(false);
@ -140,14 +152,14 @@ class ConcreteMachine:
// MARK: - CIAs. // MARK: - CIAs.
struct CIA1Handler: public MOS::MOS6526::PortHandler { struct CIAAHandler: public MOS::MOS6526::PortHandler {
} cia1_handler_; } cia_a_handler_;
struct CIA2Handler: public MOS::MOS6526::PortHandler { struct CIABHandler: public MOS::MOS6526::PortHandler {
} cia2_handler_; } cia_b_handler_;
MOS::MOS6526::MOS6526<CIA1Handler, MOS::MOS6526::Personality::P8250> cia1_; MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a_;
MOS::MOS6526::MOS6526<CIA2Handler, MOS::MOS6526::Personality::P8250> cia2_; MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b_;
// MARK: - MachineTypes::ScanProducer. // MARK: - MachineTypes::ScanProducer.