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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-19 19:16:34 +00:00

The second processor appears to be a 65c02.

This commit is contained in:
Thomas Harte
2025-11-03 21:06:34 -05:00
parent bb66033682
commit 62a6797ef3
2 changed files with 1 additions and 3 deletions
-2
View File
@@ -925,9 +925,7 @@ public:
if constexpr (is_read(operation)) {
const uint8_t result = tube_ula_.host_read(address);
value = result;
Logger::info().append("Read tube %04x: %02x", +address, result);
} else {
Logger::info().append("Write tube %04x: %02x", +address, value);
tube_ula_.host_write(address, value);
tube6502_.set_reset(tube_ula_.parasite_reset());
}
+1 -1
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@@ -83,7 +83,7 @@ private:
static constexpr auto pause_precision = CPU::MOS6502Mk2::PausePrecision::AnyCycle;
using BusHandlerT = Tube6502;
};
CPU::MOS6502Mk2::Processor<CPU::MOS6502Mk2::Model::M6502, M6502Traits> m6502_;
CPU::MOS6502Mk2::Processor<CPU::MOS6502Mk2::Model::WDC65C02, M6502Traits> m6502_;
ULAT &ula_;
};