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https://github.com/TomHarte/CLK.git
synced 2026-04-19 19:16:34 +00:00
The second processor appears to be a 65c02.
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@@ -925,9 +925,7 @@ public:
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if constexpr (is_read(operation)) {
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const uint8_t result = tube_ula_.host_read(address);
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value = result;
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Logger::info().append("Read tube %04x: %02x", +address, result);
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} else {
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Logger::info().append("Write tube %04x: %02x", +address, value);
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tube_ula_.host_write(address, value);
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tube6502_.set_reset(tube_ula_.parasite_reset());
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}
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@@ -83,7 +83,7 @@ private:
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static constexpr auto pause_precision = CPU::MOS6502Mk2::PausePrecision::AnyCycle;
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using BusHandlerT = Tube6502;
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};
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CPU::MOS6502Mk2::Processor<CPU::MOS6502Mk2::Model::M6502, M6502Traits> m6502_;
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CPU::MOS6502Mk2::Processor<CPU::MOS6502Mk2::Model::WDC65C02, M6502Traits> m6502_;
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ULAT &ula_;
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};
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