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Pull interrupt to start of hsync.
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@ -305,7 +305,7 @@ class CRTCBusHandler {
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// Per Interrupts in the CPC: "to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?";
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// if you take it as given that display mode is latched as a result of hsync then Pipe Mania seems to imply that the count
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// occurs on a leading edge and the mode lock on a trailing.
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if(was_hsync_ && !state.hsync) {
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if(!was_hsync_ && state.hsync) {
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interrupt_timer_.signal_hsync();
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}
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