6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
Code Issues Projects Releases Wiki Activity

Introduces a timing test for LSL. Which already passes.

Browse Source
This commit is contained in:
Thomas Harte 2020-01-08 22:35:28 -05:00
parent cdb31b1c2b
commit 6595f8f527
2 changed files with 30 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
OSBindings/Mac/Clock SignalTests/68000Tests.mm
View File

@ -261,6 +261,32 @@ class CPU::MC68000::ProcessorStorageTests {
XCTAssertEqual(stack_frame[6], 0x1004);
}
- (void)testShiftDuration {
//
_machine->set_program({
0x7004, // MOVE.l #$4, D0
0x7207, // MOVE.l #$7, D1
0x7401, // MOVE.l #$1, D2
0xe16e, // lsl d0, d6
0xe36e, // lsl d1, d6
0xe56e, // lsl d2, d6
});
_machine->run_for_instructions(3);
_machine->reset_cycle_count();
_machine->run_for_instructions(1);
XCTAssertEqual(_machine->get_cycle_count(), 6 + 8);
_machine->reset_cycle_count();
_machine->run_for_instructions(1);
XCTAssertEqual(_machine->get_cycle_count(), 6 + 14);
_machine->reset_cycle_count();
_machine->run_for_instructions(1);
XCTAssertEqual(_machine->get_cycle_count(), 6 + 2);
}
- (void)testOpcodeCoverage {
// Perform an audit of implemented instructions.
CPU::MC68000::ProcessorStorageTests storage_tests(

4
OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp
View File

@ -130,6 +130,10 @@ class RAM68000: public CPU::MC68000::BusHandler {
return int(duration_.as_integral()) >> 1;
}
void reset_cycle_count() {
duration_ = HalfCycles(0);
}
private:
CPU::MC68000::Processor<RAM68000, true, true> m68000_;
std::array<uint16_t, 256*1024> ram_{};