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mirror of https://github.com/TomHarte/CLK.git synced 2025-01-26 15:32:04 +00:00

Rewire MOVEP.

This commit is contained in:
Thomas Harte 2022-05-05 12:27:36 -04:00
parent 4a4e786060
commit 67462c2f92
3 changed files with 37 additions and 40 deletions

View File

@ -50,8 +50,7 @@ template <Model model, typename BusHandler> class Executor {
void jsr(uint32_t offset);
void link(uint32_t &address, uint32_t offset);
void unlink(uint32_t &address);
template <typename IntT> void movep_fromR(uint32_t reg, uint32_t address);
template <typename IntT> void movep_toR(uint32_t &reg, uint32_t address);
template <typename IntT> void movep(Preinstruction instruction, uint32_t source, uint32_t dest);
// TODO: ownership of this shouldn't be here.
struct Registers {

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@ -395,38 +395,44 @@ void Executor<model, BusHandler>::unlink(uint32_t &address) {
template <Model model, typename BusHandler>
template <typename IntT>
void Executor<model, BusHandler>::movep_fromR(uint32_t reg, uint32_t address) {
if constexpr (sizeof(IntT) == 4) {
bus_handler_.template write<uint8_t>(address, uint8_t(reg >> 24));
void Executor<model, BusHandler>::movep(Preinstruction instruction, uint32_t source, uint32_t dest) {
if(instruction.mode<0>() == AddressingMode::DataRegisterDirect) {
const uint32_t reg = source;
uint32_t address = dest;
// Move register to memory.
if constexpr (sizeof(IntT) == 4) {
bus_handler_.template write<uint8_t>(address, uint8_t(reg >> 24));
address += 2;
bus_handler_.template write<uint8_t>(address, uint8_t(reg >> 16));
address += 2;
}
bus_handler_.template write<uint8_t>(address, uint8_t(reg >> 8));
address += 2;
bus_handler_.template write<uint8_t>(address, uint8_t(reg >> 16));
address += 2;
}
bus_handler_.template write<uint8_t>(address, uint8_t(reg >> 8));
address += 2;
bus_handler_.template write<uint8_t>(address, uint8_t(reg));
}
template <Model model, typename BusHandler>
template <typename IntT>
void Executor<model, BusHandler>::movep_toR(uint32_t &reg, uint32_t address) {
if constexpr (sizeof(IntT) == 4) {
reg = bus_handler_.template read<uint8_t>(address) << 24;
address += 2;
reg |= bus_handler_.template read<uint8_t>(address) << 26;
address += 2;
bus_handler_.template write<uint8_t>(address, uint8_t(reg));
} else {
reg &= 0xffff0000;
// Move memory to register.
uint32_t &reg = data_[instruction.reg<1>()].l;
uint32_t address = source;
if constexpr (sizeof(IntT) == 4) {
reg = bus_handler_.template read<uint8_t>(address) << 24;
address += 2;
reg |= bus_handler_.template read<uint8_t>(address) << 26;
address += 2;
} else {
reg &= 0xffff0000;
}
reg |= bus_handler_.template read<uint8_t>(address) << 8;
address += 2;
reg |= bus_handler_.template read<uint8_t>(address);
}
reg |= bus_handler_.template read<uint8_t>(address) << 8;
address += 2;
reg |= bus_handler_.template read<uint8_t>(address);
}
}

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@ -1177,19 +1177,11 @@ template <
#undef set_neg_zero
case Operation::MOVEPl:
if(instruction.mode<0>() == AddressingMode::DataRegisterDirect) {
flow_controller.template movep_fromR<uint16_t>(src.l, dest.l);
} else {
flow_controller.template movep_toR<uint16_t>(src.l, dest.l);
}
flow_controller.template movep<uint32_t>(instruction, src.l, dest.l);
break;
case Operation::MOVEPw:
if(instruction.mode<0>() == AddressingMode::DataRegisterDirect) {
flow_controller.template movep_fromR<uint32_t>(src.l, dest.l);
} else {
flow_controller.template movep_toR<uint32_t>(src.l, dest.l);
}
flow_controller.template movep<uint16_t>(instruction, src.l, dest.l);
break;
/*